1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * clkgen-mux.c: ST GEN-MUX Clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 STMicroelectronics (R&D) Limited
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors: Stephen Gallimore <stephen.gallimore@st.com>
8*4882a593Smuzhiyun * Pankaj Dev <pankaj.dev@st.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/clk-provider.h>
16*4882a593Smuzhiyun #include "clkgen.h"
17*4882a593Smuzhiyun
clkgen_mux_get_parents(struct device_node * np,int * num_parents)18*4882a593Smuzhiyun static const char ** __init clkgen_mux_get_parents(struct device_node *np,
19*4882a593Smuzhiyun int *num_parents)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun const char **parents;
22*4882a593Smuzhiyun unsigned int nparents;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun nparents = of_clk_get_parent_count(np);
25*4882a593Smuzhiyun if (WARN_ON(!nparents))
26*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
29*4882a593Smuzhiyun if (!parents)
30*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun *num_parents = of_clk_parent_fill(np, parents, nparents);
33*4882a593Smuzhiyun return parents;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct clkgen_mux_data {
37*4882a593Smuzhiyun u32 offset;
38*4882a593Smuzhiyun u8 shift;
39*4882a593Smuzhiyun u8 width;
40*4882a593Smuzhiyun spinlock_t *lock;
41*4882a593Smuzhiyun unsigned long clk_flags;
42*4882a593Smuzhiyun u8 mux_flags;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct clkgen_mux_data stih407_a9_mux_data = {
46*4882a593Smuzhiyun .offset = 0x1a4,
47*4882a593Smuzhiyun .shift = 0,
48*4882a593Smuzhiyun .width = 2,
49*4882a593Smuzhiyun .lock = &clkgen_a9_lock,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
st_of_clkgen_mux_setup(struct device_node * np,struct clkgen_mux_data * data)52*4882a593Smuzhiyun static void __init st_of_clkgen_mux_setup(struct device_node *np,
53*4882a593Smuzhiyun struct clkgen_mux_data *data)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct clk *clk;
56*4882a593Smuzhiyun void __iomem *reg;
57*4882a593Smuzhiyun const char **parents;
58*4882a593Smuzhiyun int num_parents = 0;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun reg = of_iomap(np, 0);
61*4882a593Smuzhiyun if (!reg) {
62*4882a593Smuzhiyun pr_err("%s: Failed to get base address\n", __func__);
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun parents = clkgen_mux_get_parents(np, &num_parents);
67*4882a593Smuzhiyun if (IS_ERR(parents)) {
68*4882a593Smuzhiyun pr_err("%s: Failed to get parents (%ld)\n",
69*4882a593Smuzhiyun __func__, PTR_ERR(parents));
70*4882a593Smuzhiyun goto err_parents;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun clk = clk_register_mux(NULL, np->name, parents, num_parents,
74*4882a593Smuzhiyun data->clk_flags | CLK_SET_RATE_PARENT,
75*4882a593Smuzhiyun reg + data->offset,
76*4882a593Smuzhiyun data->shift, data->width, data->mux_flags,
77*4882a593Smuzhiyun data->lock);
78*4882a593Smuzhiyun if (IS_ERR(clk))
79*4882a593Smuzhiyun goto err;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun pr_debug("%s: parent %s rate %u\n",
82*4882a593Smuzhiyun __clk_get_name(clk),
83*4882a593Smuzhiyun __clk_get_name(clk_get_parent(clk)),
84*4882a593Smuzhiyun (unsigned int)clk_get_rate(clk));
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun kfree(parents);
87*4882a593Smuzhiyun of_clk_add_provider(np, of_clk_src_simple_get, clk);
88*4882a593Smuzhiyun return;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun err:
91*4882a593Smuzhiyun kfree(parents);
92*4882a593Smuzhiyun err_parents:
93*4882a593Smuzhiyun iounmap(reg);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
st_of_clkgen_a9_mux_setup(struct device_node * np)96*4882a593Smuzhiyun static void __init st_of_clkgen_a9_mux_setup(struct device_node *np)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun st_of_clkgen_mux_setup(np, &stih407_a9_mux_data);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
101*4882a593Smuzhiyun st_of_clkgen_a9_mux_setup);
102