1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun * Author: Tomasz Figa <t.figa@samsung.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Clock driver for Exynos clock output
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/syscore_ops.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define EXYNOS_CLKOUT_NR_CLKS 1
18*4882a593Smuzhiyun #define EXYNOS_CLKOUT_PARENTS 32
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define EXYNOS_PMU_DEBUG_REG 0xa00
21*4882a593Smuzhiyun #define EXYNOS_CLKOUT_DISABLE_SHIFT 0
22*4882a593Smuzhiyun #define EXYNOS_CLKOUT_MUX_SHIFT 8
23*4882a593Smuzhiyun #define EXYNOS4_CLKOUT_MUX_MASK 0xf
24*4882a593Smuzhiyun #define EXYNOS5_CLKOUT_MUX_MASK 0x1f
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct exynos_clkout {
27*4882a593Smuzhiyun struct clk_gate gate;
28*4882a593Smuzhiyun struct clk_mux mux;
29*4882a593Smuzhiyun spinlock_t slock;
30*4882a593Smuzhiyun void __iomem *reg;
31*4882a593Smuzhiyun u32 pmu_debug_save;
32*4882a593Smuzhiyun struct clk_hw_onecell_data data;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static struct exynos_clkout *clkout;
36*4882a593Smuzhiyun
exynos_clkout_suspend(void)37*4882a593Smuzhiyun static int exynos_clkout_suspend(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
exynos_clkout_resume(void)44*4882a593Smuzhiyun static void exynos_clkout_resume(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static struct syscore_ops exynos_clkout_syscore_ops = {
50*4882a593Smuzhiyun .suspend = exynos_clkout_suspend,
51*4882a593Smuzhiyun .resume = exynos_clkout_resume,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
exynos_clkout_init(struct device_node * node,u32 mux_mask)54*4882a593Smuzhiyun static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun const char *parent_names[EXYNOS_CLKOUT_PARENTS];
57*4882a593Smuzhiyun struct clk *parents[EXYNOS_CLKOUT_PARENTS];
58*4882a593Smuzhiyun int parent_count;
59*4882a593Smuzhiyun int ret;
60*4882a593Smuzhiyun int i;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
63*4882a593Smuzhiyun GFP_KERNEL);
64*4882a593Smuzhiyun if (!clkout)
65*4882a593Smuzhiyun return;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun spin_lock_init(&clkout->slock);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun parent_count = 0;
70*4882a593Smuzhiyun for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
71*4882a593Smuzhiyun char name[] = "clkoutXX";
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun snprintf(name, sizeof(name), "clkout%d", i);
74*4882a593Smuzhiyun parents[i] = of_clk_get_by_name(node, name);
75*4882a593Smuzhiyun if (IS_ERR(parents[i])) {
76*4882a593Smuzhiyun parent_names[i] = "none";
77*4882a593Smuzhiyun continue;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun parent_names[i] = __clk_get_name(parents[i]);
81*4882a593Smuzhiyun parent_count = i + 1;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (!parent_count)
85*4882a593Smuzhiyun goto free_clkout;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun clkout->reg = of_iomap(node, 0);
88*4882a593Smuzhiyun if (!clkout->reg)
89*4882a593Smuzhiyun goto clks_put;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
92*4882a593Smuzhiyun clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
93*4882a593Smuzhiyun clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
94*4882a593Smuzhiyun clkout->gate.lock = &clkout->slock;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
97*4882a593Smuzhiyun clkout->mux.mask = mux_mask;
98*4882a593Smuzhiyun clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
99*4882a593Smuzhiyun clkout->mux.lock = &clkout->slock;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
102*4882a593Smuzhiyun parent_names, parent_count, &clkout->mux.hw,
103*4882a593Smuzhiyun &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
104*4882a593Smuzhiyun &clk_gate_ops, CLK_SET_RATE_PARENT
105*4882a593Smuzhiyun | CLK_SET_RATE_NO_REPARENT);
106*4882a593Smuzhiyun if (IS_ERR(clkout->data.hws[0]))
107*4882a593Smuzhiyun goto err_unmap;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
110*4882a593Smuzhiyun ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data);
111*4882a593Smuzhiyun if (ret)
112*4882a593Smuzhiyun goto err_clk_unreg;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun register_syscore_ops(&exynos_clkout_syscore_ops);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun err_clk_unreg:
119*4882a593Smuzhiyun clk_hw_unregister(clkout->data.hws[0]);
120*4882a593Smuzhiyun err_unmap:
121*4882a593Smuzhiyun iounmap(clkout->reg);
122*4882a593Smuzhiyun clks_put:
123*4882a593Smuzhiyun for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
124*4882a593Smuzhiyun if (!IS_ERR(parents[i]))
125*4882a593Smuzhiyun clk_put(parents[i]);
126*4882a593Smuzhiyun free_clkout:
127*4882a593Smuzhiyun kfree(clkout);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun pr_err("%s: failed to register clkout clock\n", __func__);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting
134*4882a593Smuzhiyun * the OF_POPULATED flag on the pmu device tree node, so later the
135*4882a593Smuzhiyun * Exynos PMU platform device can be properly probed with PMU driver.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun
exynos4_clkout_init(struct device_node * node)138*4882a593Smuzhiyun static void __init exynos4_clkout_init(struct device_node *node)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
143*4882a593Smuzhiyun exynos4_clkout_init);
144*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
145*4882a593Smuzhiyun exynos4_clkout_init);
146*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
147*4882a593Smuzhiyun exynos4_clkout_init);
148*4882a593Smuzhiyun
exynos5_clkout_init(struct device_node * node)149*4882a593Smuzhiyun static void __init exynos5_clkout_init(struct device_node *node)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu",
154*4882a593Smuzhiyun exynos5_clkout_init);
155*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu",
156*4882a593Smuzhiyun exynos5_clkout_init);
157*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu",
158*4882a593Smuzhiyun exynos5_clkout_init);
159*4882a593Smuzhiyun CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu",
160*4882a593Smuzhiyun exynos5_clkout_init);
161