1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2018 NXP
4*4882a593Smuzhiyun * Dong Aisheng <aisheng.dong@nxp.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __IMX_CLK_SCU_H
8*4882a593Smuzhiyun #define __IMX_CLK_SCU_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/firmware/imx/sci.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun int imx_clk_scu_init(void);
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
15*4882a593Smuzhiyun int num_parents, u32 rsrc_id, u8 clk_type);
16*4882a593Smuzhiyun
imx_clk_scu(const char * name,u32 rsrc_id,u8 clk_type)17*4882a593Smuzhiyun static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
18*4882a593Smuzhiyun u8 clk_type)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun return __imx_clk_scu(name, NULL, 0, rsrc_id, clk_type);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
imx_clk_scu2(const char * name,const char * const * parents,int num_parents,u32 rsrc_id,u8 clk_type)23*4882a593Smuzhiyun static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
24*4882a593Smuzhiyun int num_parents, u32 rsrc_id, u8 clk_type)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun return __imx_clk_scu(name, parents, num_parents, rsrc_id, clk_type);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
30*4882a593Smuzhiyun unsigned long flags, void __iomem *reg,
31*4882a593Smuzhiyun u8 bit_idx, bool hw_gate);
32*4882a593Smuzhiyun #endif
33