1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016-2018 Xilinx 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __LINUX_CLK_ZYNQMP_H_ 7*4882a593Smuzhiyun #define __LINUX_CLK_ZYNQMP_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/spinlock.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/firmware/xlnx-zynqmp.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum topology_type { 14*4882a593Smuzhiyun TYPE_INVALID, 15*4882a593Smuzhiyun TYPE_MUX, 16*4882a593Smuzhiyun TYPE_PLL, 17*4882a593Smuzhiyun TYPE_FIXEDFACTOR, 18*4882a593Smuzhiyun TYPE_DIV1, 19*4882a593Smuzhiyun TYPE_DIV2, 20*4882a593Smuzhiyun TYPE_GATE, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /** 24*4882a593Smuzhiyun * struct clock_topology - Clock topology 25*4882a593Smuzhiyun * @type: Type of topology 26*4882a593Smuzhiyun * @flag: Topology flags 27*4882a593Smuzhiyun * @type_flag: Topology type specific flag 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun struct clock_topology { 30*4882a593Smuzhiyun u32 type; 31*4882a593Smuzhiyun u32 flag; 32*4882a593Smuzhiyun u32 type_flag; 33*4882a593Smuzhiyun u8 custom_type_flag; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, 37*4882a593Smuzhiyun const char * const *parents, 38*4882a593Smuzhiyun u8 num_parents, 39*4882a593Smuzhiyun const struct clock_topology *nodes); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, 42*4882a593Smuzhiyun const char * const *parents, 43*4882a593Smuzhiyun u8 num_parents, 44*4882a593Smuzhiyun const struct clock_topology *nodes); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct clk_hw *zynqmp_clk_register_divider(const char *name, 47*4882a593Smuzhiyun u32 clk_id, 48*4882a593Smuzhiyun const char * const *parents, 49*4882a593Smuzhiyun u8 num_parents, 50*4882a593Smuzhiyun const struct clock_topology *nodes); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, 53*4882a593Smuzhiyun const char * const *parents, 54*4882a593Smuzhiyun u8 num_parents, 55*4882a593Smuzhiyun const struct clock_topology *nodes); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, 58*4882a593Smuzhiyun u32 clk_id, 59*4882a593Smuzhiyun const char * const *parents, 60*4882a593Smuzhiyun u8 num_parents, 61*4882a593Smuzhiyun const struct clock_topology *nodes); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif 64