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Searched refs:divider (Results 1 – 25 of 325) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Ddivider.c40 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
53 max_val = divider->max; in _setup_mask()
55 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
56 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
60 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
65 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
68 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
70 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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H A Dclk-dra7-atl.c57 u32 divider; /* Cached divider value */ member
93 cdesc->divider - 1); in atl_clk_enable()
128 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
134 unsigned divider; in atl_clk_round_rate() local
136 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
138 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
140 return *parent_rate / divider; in atl_clk_round_rate()
147 u32 divider; in atl_clk_set_rate() local
153 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-divider.c28 struct clk_regmap_divider *divider = to_clk_regmap_divider(hw); in clk_regmap_divider_recalc_rate() local
31 regmap_read(divider->regmap, divider->reg, &val); in clk_regmap_divider_recalc_rate()
33 div = val >> divider->shift; in clk_regmap_divider_recalc_rate()
34 div &= div_mask(divider->width); in clk_regmap_divider_recalc_rate()
37 CLK_DIVIDER_ROUND_CLOSEST, divider->width); in clk_regmap_divider_recalc_rate()
44 struct clk_regmap_divider *divider = to_clk_regmap_divider(hw); in clk_regmap_divider_round_rate() local
46 return divider_round_rate(hw, rate, prate, NULL, divider->width, in clk_regmap_divider_round_rate()
68 struct clk_regmap_divider *divider = to_clk_regmap_divider(hw); in clk_regmap_divider_set_rate() local
73 dev_dbg(divider->dev, "%s: parent_rate=%ld, div=%d, rate=%ld\n", in clk_regmap_divider_set_rate()
76 val = div_mask(divider->width) << (divider->shift + 16); in clk_regmap_divider_set_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-regmap-divider.c21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Ddove-divider.c53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
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/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c18 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_recalc_rate() local
21 val = clk_readl(divider->reg) >> divider->shift; in clk_dclk_recalc_rate()
22 val &= div_mask(divider->width); in clk_dclk_recalc_rate()
30 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_round_rate() local
31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate()
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
44 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_set_rate() local
49 value = divider_get_val(rate, parent_rate, divider->table, in clk_dclk_set_rate()
50 divider->width, divider->flags); in clk_dclk_set_rate()
52 if (divider->lock) in clk_dclk_set_rate()
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H A Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
90 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
94 divider->width, in clk_half_divider_round_rate()
95 divider->flags); in clk_half_divider_round_rate()
103 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
110 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
112 if (divider->lock) in clk_half_divider_set_rate()
113 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-divider.c28 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
30 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
31 return ioread32be(divider->reg); in clk_div_readl()
33 return readl(divider->reg); in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
38 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
39 iowrite32be(val, divider->reg); in clk_div_writel()
41 writel(val, divider->reg); in clk_div_writel()
151 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
154 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
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H A Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-fixup-div.c24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
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H A Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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H A Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
/OK3568_Linux_fs/kernel/drivers/clk/mxs/
H A Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
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/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A Ddivider.c81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
83 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
84 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
114 struct zynqmp_clk_divider *divider, in zynqmp_get_divider2_val() argument
136 for (div2 = 1; div2 <= divider->max_div;) { in zynqmp_get_divider2_val()
143 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_get_divider2_val()
167 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
169 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/baikal-t1/
H A Dccu-div.c79 unsigned long divider) in ccu_div_var_update_clkdiv() argument
86 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
212 unsigned long divider; in ccu_div_var_recalc_rate() local
216 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
218 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
225 unsigned long divider; in ccu_div_var_calc_divider() local
227 divider = parent_rate / rate; in ccu_div_var_calc_divider()
228 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
236 unsigned long divider; in ccu_div_var_round_rate() local
238 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask); in ccu_div_var_round_rate()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/afe/
H A Dvoltage-divider.txt1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
/OK3568_Linux_fs/kernel/drivers/clk/davinci/
H A Dpll.c244 struct clk_divider *divider; in davinci_pll_div_register() local
255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
262 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
263 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
266 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
271 NULL, NULL, &divider->hw, divider_ops, in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
579 struct clk_divider *divider; in davinci_pll_obsclk_register() local
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/
H A Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
79 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
85 compatible = "ti,divider-clock";
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/OK3568_Linux_fs/kernel/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c145 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
148 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
158 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
160 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
170 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
174 (divider + 1) * rollovers); in clock_divider_to_freq()
215 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
222 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
226 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
235 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
/OK3568_Linux_fs/kernel/drivers/clk/x86/
H A Dclk-cgu.c138 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_recalc_rate() local
142 spin_lock_irqsave(&divider->lock, flags); in lgm_clk_divider_recalc_rate()
143 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
144 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
145 spin_unlock_irqrestore(&divider->lock, flags); in lgm_clk_divider_recalc_rate()
147 return divider_recalc_rate(hw, parent_rate, val, divider->table, in lgm_clk_divider_recalc_rate()
148 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
155 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_round_rate() local
157 return divider_round_rate(hw, rate, prate, divider->table, in lgm_clk_divider_round_rate()
158 divider->width, divider->flags); in lgm_clk_divider_round_rate()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
100 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
101 divider++; in clk_bcm2835_i2c_calc_divider()
102 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
103 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
106 return divider; in clk_bcm2835_i2c_calc_divider()
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); in clk_bcm2835_i2c_set_rate() local
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
126 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra7xx-clocks.dtsi211 compatible = "ti,divider-clock";
222 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
300 compatible = "ti,divider-clock";
344 compatible = "ti,divider-clock";
382 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
433 compatible = "ti,divider-clock";
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx23885/
H A Dcx23888-ir.c184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
193 (divider + 1) * rollovers); in clock_divider_to_freq()
234 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) in pulse_width_count_to_us() argument
270 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ in pulse_width_count_to_us()
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