184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)  in clock_divider_to_carrier_freq()  argument
186 	return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);  in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider,  in clock_divider_to_freq()  argument
193 				 (divider + 1) * rollovers);  in clock_divider_to_freq()
234 static u32 clock_divider_to_resolution(u16 divider)  in clock_divider_to_resolution()  argument
241 	return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,  in clock_divider_to_resolution()
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider)  in pulse_width_count_to_ns()  argument
254 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */  in pulse_width_count_to_ns()
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)  in pulse_width_count_to_us()  argument
270 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */  in pulse_width_count_to_us()
413 				       u16 *divider)  in txclk_tx_s_carrier()  argument
415 	*divider = carrier_freq_to_clock_divider(freq);  in txclk_tx_s_carrier()
416 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);  in txclk_tx_s_carrier()
417 	return clock_divider_to_carrier_freq(*divider);  in txclk_tx_s_carrier()
422 				       u16 *divider)  in rxclk_rx_s_carrier()  argument
424 	*divider = carrier_freq_to_clock_divider(freq);  in rxclk_rx_s_carrier()
425 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);  in rxclk_rx_s_carrier()
426 	return clock_divider_to_carrier_freq(*divider);  in rxclk_rx_s_carrier()
430 				      u16 *divider)  in txclk_tx_s_max_pulse_width()  argument
437 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);  in txclk_tx_s_max_pulse_width()
438 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);  in txclk_tx_s_max_pulse_width()
439 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);  in txclk_tx_s_max_pulse_width()
443 				      u16 *divider)  in rxclk_rx_s_max_pulse_width()  argument
450 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);  in rxclk_rx_s_max_pulse_width()
451 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);  in rxclk_rx_s_max_pulse_width()
452 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);  in rxclk_rx_s_max_pulse_width()
634 	u16 divider = (u16) atomic_read(&state->rxclk_divider);  in cx23888_ir_rx_read()  local
666 				  (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;  in cx23888_ir_rx_read()