xref: /OK3568_Linux_fs/kernel/drivers/clk/qcom/clk-regmap-divider.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/bitops.h>
8*4882a593Smuzhiyun #include <linux/regmap.h>
9*4882a593Smuzhiyun #include <linux/export.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include "clk-regmap-divider.h"
12*4882a593Smuzhiyun 
to_clk_regmap_div(struct clk_hw * hw)13*4882a593Smuzhiyun static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun 	return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
16*4882a593Smuzhiyun }
17*4882a593Smuzhiyun 
div_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)18*4882a593Smuzhiyun static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
19*4882a593Smuzhiyun 			      unsigned long *prate)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	struct clk_regmap_div *divider = to_clk_regmap_div(hw);
22*4882a593Smuzhiyun 	struct clk_regmap *clkr = &divider->clkr;
23*4882a593Smuzhiyun 	u32 val;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	regmap_read(clkr->regmap, divider->reg, &val);
26*4882a593Smuzhiyun 	val >>= divider->shift;
27*4882a593Smuzhiyun 	val &= BIT(divider->width) - 1;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
30*4882a593Smuzhiyun 				     CLK_DIVIDER_ROUND_CLOSEST, val);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun 
div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)33*4882a593Smuzhiyun static long div_round_rate(struct clk_hw *hw, unsigned long rate,
34*4882a593Smuzhiyun 			   unsigned long *prate)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	struct clk_regmap_div *divider = to_clk_regmap_div(hw);
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	return divider_round_rate(hw, rate, prate, NULL, divider->width,
39*4882a593Smuzhiyun 				  CLK_DIVIDER_ROUND_CLOSEST);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun 
div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)42*4882a593Smuzhiyun static int div_set_rate(struct clk_hw *hw, unsigned long rate,
43*4882a593Smuzhiyun 			unsigned long parent_rate)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	struct clk_regmap_div *divider = to_clk_regmap_div(hw);
46*4882a593Smuzhiyun 	struct clk_regmap *clkr = &divider->clkr;
47*4882a593Smuzhiyun 	u32 div;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	div = divider_get_val(rate, parent_rate, NULL, divider->width,
50*4882a593Smuzhiyun 			      CLK_DIVIDER_ROUND_CLOSEST);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return regmap_update_bits(clkr->regmap, divider->reg,
53*4882a593Smuzhiyun 				  (BIT(divider->width) - 1) << divider->shift,
54*4882a593Smuzhiyun 				  div << divider->shift);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)57*4882a593Smuzhiyun static unsigned long div_recalc_rate(struct clk_hw *hw,
58*4882a593Smuzhiyun 				     unsigned long parent_rate)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	struct clk_regmap_div *divider = to_clk_regmap_div(hw);
61*4882a593Smuzhiyun 	struct clk_regmap *clkr = &divider->clkr;
62*4882a593Smuzhiyun 	u32 div;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	regmap_read(clkr->regmap, divider->reg, &div);
65*4882a593Smuzhiyun 	div >>= divider->shift;
66*4882a593Smuzhiyun 	div &= BIT(divider->width) - 1;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	return divider_recalc_rate(hw, parent_rate, div, NULL,
69*4882a593Smuzhiyun 				   CLK_DIVIDER_ROUND_CLOSEST, divider->width);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun const struct clk_ops clk_regmap_div_ops = {
73*4882a593Smuzhiyun 	.round_rate = div_round_rate,
74*4882a593Smuzhiyun 	.set_rate = div_set_rate,
75*4882a593Smuzhiyun 	.recalc_rate = div_recalc_rate,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun const struct clk_ops clk_regmap_div_ro_ops = {
80*4882a593Smuzhiyun 	.round_rate = div_round_ro_rate,
81*4882a593Smuzhiyun 	.recalc_rate = div_recalc_rate,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
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