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Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8135-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
H A Dmt7629-clk.h85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
H A Dmt8516-clk.h171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
H A Dmt7622-clk.h70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
H A Dmt8173-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
H A Dmt2701-clk.h88 #define CLK_TOP_DDRPHYCFG_SEL 77 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt7629.c491 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
595 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
H A Dclk-mt7622.c519 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
641 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
H A Dclk-mt8173.c544 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
832 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_clk_enable_critical()
H A Dclk-mt8135.c381 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
H A Dclk-mt2701.c492 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
H A Dclk-mt8167.c558 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,