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Searched refs:BIT_5 (Results 1 – 23 of 23) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/net/ethernet/realtek/r8168/
H A Dr8168_dash.h187 #define TXS_LNKF BIT_5
226 #define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5
H A Dr8168_n.c3197 if (RTL_R8(tp, 0xF2) & BIT_5) in rtl8168_is_phy_disable_mode_enabled()
4278 if (tp->org_pci_offset_99 & (BIT_5 | BIT_6)) in rtl8168_enable_pci_offset_99()
6114 data |= (BIT_4 | BIT_5 | BIT_6); in rtl8168_enable_EEE()
6139 data |= (BIT_4 | BIT_5 | BIT_6); in rtl8168_enable_EEE()
8933 csi_tmp |= ( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 ); in rtl8168_hw_init()
8985 BIT_5 in rtl8168_hw_ephy_config()
9112 ephy_data |= (BIT_2 | BIT_5 | BIT_9); in rtl8168_hw_ephy_config()
9119 … ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); in rtl8168_hw_ephy_config()
9128 ephy_data |= BIT_5; in rtl8168_hw_ephy_config()
9143 ephy_data |= (BIT_2 | BIT_5 | BIT_9); in rtl8168_hw_ephy_config()
[all …]
H A Dr8168.h1395 BIT_5 = (1 << 5), enumerator
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dqla1280.h22 #define BIT_5 0x20 macro
125 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */
128 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
129 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
312 #define TP_PPR BIT_5 /* PPR */
H A Dqla1280.c445 return BIT_5; in qla1280_data_direction()
449 return BIT_5 | BIT_6; in qla1280_data_direction()
1922 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()
2191 cfg1 = RD_REG_WORD(&reg->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2263 mb[1] |= BIT_5; in qla1280_nvram_config()
2268 mb[2] |= BIT_5; in qla1280_nvram_config()
3913 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2) in qla1280_get_target_parameters()
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_fw.h23 #define FO2_ENABLE_SEL_CLASS2 BIT_5
43 #define PDF_FCP2_CONF BIT_5
901 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
902 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
1160 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1201 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1482 VP_FLAGS_NAME_VALID = BIT_5,
H A Dqla_target.h85 #define OF_EXPL_CONF BIT_5 /* Explicit Confirmation Requested */
466 #define CTIO7_FLAGS_EXPLICIT_CONFORM BIT_5
735 #define NOTIFY_ACK_CLEAR_LIP_RESET BIT_5
834 TRC_XMIT_STATUS = BIT_5,
H A Dqla_def.h86 #define BIT_5 0x20 macro
370 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
814 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
1127 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1148 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1302 #define MBX_5 BIT_5
1896 #define CF_READ BIT_5
1964 #define PO_DISABLE_INCR_REF_TAG BIT_5
2056 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2481 #define NVME_PRLI_SP_INITIATOR BIT_5
[all …]
H A Dqla_init.c4001 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()
4008 ha->fw_options[10] |= BIT_5 | in qla2x00_update_fw_options()
4014 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()
4019 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()
4026 ha->fw_options[11] |= BIT_5 | in qla2x00_update_fw_options()
4745 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()
4746 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()
4747 nv->add_firmware_options[1] = BIT_5 | BIT_4; in qla2x00_nvram_config()
4752 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()
4753 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()
[all …]
H A Dqla_mid.c753 options |= BIT_5; in qla25xx_create_req_que()
871 options |= BIT_5; in qla25xx_create_rsp_que()
H A Dqla_mbx.c705 mcp->in_mb |= BIT_5; in qla2x00_execute_fw()
2302 mcp->mb[1] |= BIT_5; in qla24xx_link_initialize()
4193 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()
6272 if (!(subcode & (BIT_2 | BIT_5))) in qla83xx_access_control()
6285 if (subcode & BIT_5) in qla83xx_access_control()
6568 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0) in __qla24xx_parse_gpdb()
H A Dqla_target.c6869 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_24xx_config_nvram_stage1()
6896 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_24xx_config_nvram_stage1()
6975 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_81xx_config_nvram_stage1()
7000 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_81xx_config_nvram_stage1()
7062 vpmod->options_idx1 &= ~BIT_5; in qlt_modify_vp_config()
H A Dqla_sup.c2149 if ((flash_data & BIT_5) && cnt > 2) in qla2x00_poll_flash()
H A Dqla_isr.c2150 } else if (iop[0] & BIT_5) in qla24xx_logio_entry()
H A Dqla_os.c5938 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) in qla24xx_process_purex_rdp()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_ctx.c1366 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()
1370 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()
1421 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); in qlcnic_get_eswitch_port_config()
H A Dqlcnic_hdr.h200 #define BIT_5 0x20 macro
H A Dqlcnic_minidump.c28 #define QLCNIC_DUMP_RD_SAVE BIT_5
H A Dqlcnic.h923 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
H A Dqlcnic_sriov_common.c388 if (status & BIT_5) in qlcnic_sriov_get_vf_vport_info()
H A Dqlcnic_io.c367 #define QLCNIC_ENCAP_DO_L4_CSUM BIT_5
/OK3568_Linux_fs/kernel/drivers/scsi/qla4xxx/
H A Dql4_def.h86 #define BIT_5 0x20 macro
H A Dql4_os.c3670 SET_BITVAL(sess->discovery_logout_en, options, BIT_5); in qla4xxx_copy_to_fwddb_param()
3679 SET_BITVAL(conn->tcp_nagle_disable, options, BIT_5); in qla4xxx_copy_to_fwddb_param()