1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * QLogic qlcnic NIC Driver
4*4882a593Smuzhiyun * Copyright (c) 2009-2013 QLogic Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "qlcnic.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
10*4882a593Smuzhiyun {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
11*4882a593Smuzhiyun {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
12*4882a593Smuzhiyun {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
13*4882a593Smuzhiyun {QLCNIC_CMD_DESTROY_TX_CTX, 3, 1},
14*4882a593Smuzhiyun {QLCNIC_CMD_INTRPT_TEST, 4, 1},
15*4882a593Smuzhiyun {QLCNIC_CMD_SET_MTU, 4, 1},
16*4882a593Smuzhiyun {QLCNIC_CMD_READ_PHY, 4, 2},
17*4882a593Smuzhiyun {QLCNIC_CMD_WRITE_PHY, 5, 1},
18*4882a593Smuzhiyun {QLCNIC_CMD_READ_HW_REG, 4, 1},
19*4882a593Smuzhiyun {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
20*4882a593Smuzhiyun {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
21*4882a593Smuzhiyun {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
22*4882a593Smuzhiyun {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
23*4882a593Smuzhiyun {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
24*4882a593Smuzhiyun {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
25*4882a593Smuzhiyun {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
26*4882a593Smuzhiyun {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
27*4882a593Smuzhiyun {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
28*4882a593Smuzhiyun {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
29*4882a593Smuzhiyun {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
30*4882a593Smuzhiyun {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
31*4882a593Smuzhiyun {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
32*4882a593Smuzhiyun {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
33*4882a593Smuzhiyun {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
34*4882a593Smuzhiyun {QLCNIC_CMD_GET_ESWITCH_STATS, 4, 1},
35*4882a593Smuzhiyun {QLCNIC_CMD_CONFIG_PORT, 4, 1},
36*4882a593Smuzhiyun {QLCNIC_CMD_TEMP_SIZE, 4, 4},
37*4882a593Smuzhiyun {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
38*4882a593Smuzhiyun {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
39*4882a593Smuzhiyun {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
40*4882a593Smuzhiyun {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
41*4882a593Smuzhiyun {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
42*4882a593Smuzhiyun {QLCNIC_CMD_DCB_QUERY_PARAM, 4, 1},
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
qlcnic_get_cmd_signature(struct qlcnic_hardware_context * ahw)45*4882a593Smuzhiyun static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
48*4882a593Smuzhiyun (0xcafe << 16);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Allocate mailbox registers */
qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args * mbx,struct qlcnic_adapter * adapter,u32 type)52*4882a593Smuzhiyun int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
53*4882a593Smuzhiyun struct qlcnic_adapter *adapter, u32 type)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun int i, size;
56*4882a593Smuzhiyun const struct qlcnic_mailbox_metadata *mbx_tbl;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun mbx_tbl = qlcnic_mbx_tbl;
59*4882a593Smuzhiyun size = ARRAY_SIZE(qlcnic_mbx_tbl);
60*4882a593Smuzhiyun for (i = 0; i < size; i++) {
61*4882a593Smuzhiyun if (type == mbx_tbl[i].cmd) {
62*4882a593Smuzhiyun mbx->req.num = mbx_tbl[i].in_args;
63*4882a593Smuzhiyun mbx->rsp.num = mbx_tbl[i].out_args;
64*4882a593Smuzhiyun mbx->req.arg = kcalloc(mbx->req.num,
65*4882a593Smuzhiyun sizeof(u32), GFP_ATOMIC);
66*4882a593Smuzhiyun if (!mbx->req.arg)
67*4882a593Smuzhiyun return -ENOMEM;
68*4882a593Smuzhiyun mbx->rsp.arg = kcalloc(mbx->rsp.num,
69*4882a593Smuzhiyun sizeof(u32), GFP_ATOMIC);
70*4882a593Smuzhiyun if (!mbx->rsp.arg) {
71*4882a593Smuzhiyun kfree(mbx->req.arg);
72*4882a593Smuzhiyun mbx->req.arg = NULL;
73*4882a593Smuzhiyun return -ENOMEM;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun mbx->req.arg[0] = type;
76*4882a593Smuzhiyun break;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Free up mailbox registers */
qlcnic_free_mbx_args(struct qlcnic_cmd_args * cmd)83*4882a593Smuzhiyun void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun kfree(cmd->req.arg);
86*4882a593Smuzhiyun cmd->req.arg = NULL;
87*4882a593Smuzhiyun kfree(cmd->rsp.arg);
88*4882a593Smuzhiyun cmd->rsp.arg = NULL;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static u32
qlcnic_poll_rsp(struct qlcnic_adapter * adapter)92*4882a593Smuzhiyun qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun u32 rsp;
95*4882a593Smuzhiyun int timeout = 0, err = 0;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun do {
98*4882a593Smuzhiyun /* give atleast 1ms for firmware to respond */
99*4882a593Smuzhiyun mdelay(1);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
102*4882a593Smuzhiyun return QLCNIC_CDRP_RSP_TIMEOUT;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
105*4882a593Smuzhiyun } while (!QLCNIC_CDRP_IS_RSP(rsp));
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return rsp;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
qlcnic_82xx_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)110*4882a593Smuzhiyun int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
111*4882a593Smuzhiyun struct qlcnic_cmd_args *cmd)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun int i, err = 0;
114*4882a593Smuzhiyun u32 rsp;
115*4882a593Smuzhiyun u32 signature;
116*4882a593Smuzhiyun struct pci_dev *pdev = adapter->pdev;
117*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
118*4882a593Smuzhiyun const char *fmt;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun signature = qlcnic_get_cmd_signature(ahw);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Acquire semaphore before accessing CRB */
123*4882a593Smuzhiyun if (qlcnic_api_lock(adapter)) {
124*4882a593Smuzhiyun cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
125*4882a593Smuzhiyun return cmd->rsp.arg[0];
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
129*4882a593Smuzhiyun for (i = 1; i < cmd->req.num; i++)
130*4882a593Smuzhiyun QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
131*4882a593Smuzhiyun QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
132*4882a593Smuzhiyun QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
133*4882a593Smuzhiyun rsp = qlcnic_poll_rsp(adapter);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
136*4882a593Smuzhiyun dev_err(&pdev->dev, "command timeout, response = 0x%x\n", rsp);
137*4882a593Smuzhiyun cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
138*4882a593Smuzhiyun } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
139*4882a593Smuzhiyun cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
140*4882a593Smuzhiyun switch (cmd->rsp.arg[0]) {
141*4882a593Smuzhiyun case QLCNIC_RCODE_INVALID_ARGS:
142*4882a593Smuzhiyun fmt = "CDRP invalid args: [%d]\n";
143*4882a593Smuzhiyun break;
144*4882a593Smuzhiyun case QLCNIC_RCODE_NOT_SUPPORTED:
145*4882a593Smuzhiyun case QLCNIC_RCODE_NOT_IMPL:
146*4882a593Smuzhiyun fmt = "CDRP command not supported: [%d]\n";
147*4882a593Smuzhiyun break;
148*4882a593Smuzhiyun case QLCNIC_RCODE_NOT_PERMITTED:
149*4882a593Smuzhiyun fmt = "CDRP requested action not permitted: [%d]\n";
150*4882a593Smuzhiyun break;
151*4882a593Smuzhiyun case QLCNIC_RCODE_INVALID:
152*4882a593Smuzhiyun fmt = "CDRP invalid or unknown cmd received: [%d]\n";
153*4882a593Smuzhiyun break;
154*4882a593Smuzhiyun case QLCNIC_RCODE_TIMEOUT:
155*4882a593Smuzhiyun fmt = "CDRP command timeout: [%d]\n";
156*4882a593Smuzhiyun break;
157*4882a593Smuzhiyun default:
158*4882a593Smuzhiyun fmt = "CDRP command failed: [%d]\n";
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
162*4882a593Smuzhiyun qlcnic_dump_mbx(adapter, cmd);
163*4882a593Smuzhiyun } else if (rsp == QLCNIC_CDRP_RSP_OK)
164*4882a593Smuzhiyun cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun for (i = 1; i < cmd->rsp.num; i++)
167*4882a593Smuzhiyun cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* Release semaphore */
170*4882a593Smuzhiyun qlcnic_api_unlock(adapter);
171*4882a593Smuzhiyun return cmd->rsp.arg[0];
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter * adapter,u32 fw_cmd)174*4882a593Smuzhiyun int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
177*4882a593Smuzhiyun u32 arg1, arg2, arg3;
178*4882a593Smuzhiyun char drv_string[12];
179*4882a593Smuzhiyun int err = 0;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun memset(drv_string, 0, sizeof(drv_string));
182*4882a593Smuzhiyun snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
183*4882a593Smuzhiyun _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
184*4882a593Smuzhiyun _QLCNIC_LINUX_SUBVERSION);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
187*4882a593Smuzhiyun if (err)
188*4882a593Smuzhiyun return err;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun memcpy(&arg1, drv_string, sizeof(u32));
191*4882a593Smuzhiyun memcpy(&arg2, drv_string + 4, sizeof(u32));
192*4882a593Smuzhiyun memcpy(&arg3, drv_string + 8, sizeof(u32));
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun cmd.req.arg[1] = arg1;
195*4882a593Smuzhiyun cmd.req.arg[2] = arg2;
196*4882a593Smuzhiyun cmd.req.arg[3] = arg3;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
199*4882a593Smuzhiyun if (err) {
200*4882a593Smuzhiyun dev_info(&adapter->pdev->dev,
201*4882a593Smuzhiyun "Failed to set driver version in firmware\n");
202*4882a593Smuzhiyun err = -EIO;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
205*4882a593Smuzhiyun return err;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun int
qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter * adapter,int mtu)209*4882a593Smuzhiyun qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun int err = 0;
212*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
213*4882a593Smuzhiyun struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
216*4882a593Smuzhiyun return err;
217*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
218*4882a593Smuzhiyun if (err)
219*4882a593Smuzhiyun return err;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun cmd.req.arg[1] = recv_ctx->context_id;
222*4882a593Smuzhiyun cmd.req.arg[2] = mtu;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
225*4882a593Smuzhiyun if (err) {
226*4882a593Smuzhiyun dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
227*4882a593Smuzhiyun err = -EIO;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
230*4882a593Smuzhiyun return err;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter * adapter)233*4882a593Smuzhiyun int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
236*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
237*4882a593Smuzhiyun dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
238*4882a593Smuzhiyun struct net_device *netdev = adapter->netdev;
239*4882a593Smuzhiyun u32 temp_intr_crb_mode, temp_rds_crb_mode;
240*4882a593Smuzhiyun struct qlcnic_cardrsp_rds_ring *prsp_rds;
241*4882a593Smuzhiyun struct qlcnic_cardrsp_sds_ring *prsp_sds;
242*4882a593Smuzhiyun struct qlcnic_hostrq_rds_ring *prq_rds;
243*4882a593Smuzhiyun struct qlcnic_hostrq_sds_ring *prq_sds;
244*4882a593Smuzhiyun struct qlcnic_host_rds_ring *rds_ring;
245*4882a593Smuzhiyun struct qlcnic_host_sds_ring *sds_ring;
246*4882a593Smuzhiyun struct qlcnic_cardrsp_rx_ctx *prsp;
247*4882a593Smuzhiyun struct qlcnic_hostrq_rx_ctx *prq;
248*4882a593Smuzhiyun u8 i, nrds_rings, nsds_rings;
249*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
250*4882a593Smuzhiyun size_t rq_size, rsp_size;
251*4882a593Smuzhiyun u32 cap, reg, val, reg2;
252*4882a593Smuzhiyun u64 phys_addr;
253*4882a593Smuzhiyun u16 temp_u16;
254*4882a593Smuzhiyun void *addr;
255*4882a593Smuzhiyun int err;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun nrds_rings = adapter->max_rds_rings;
258*4882a593Smuzhiyun nsds_rings = adapter->drv_sds_rings;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
261*4882a593Smuzhiyun nsds_rings);
262*4882a593Smuzhiyun rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
263*4882a593Smuzhiyun nsds_rings);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
266*4882a593Smuzhiyun &hostrq_phys_addr, GFP_KERNEL);
267*4882a593Smuzhiyun if (addr == NULL)
268*4882a593Smuzhiyun return -ENOMEM;
269*4882a593Smuzhiyun prq = addr;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
272*4882a593Smuzhiyun &cardrsp_phys_addr, GFP_KERNEL);
273*4882a593Smuzhiyun if (addr == NULL) {
274*4882a593Smuzhiyun err = -ENOMEM;
275*4882a593Smuzhiyun goto out_free_rq;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun prsp = addr;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
282*4882a593Smuzhiyun | QLCNIC_CAP0_VALIDOFF);
283*4882a593Smuzhiyun cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) &&
286*4882a593Smuzhiyun !adapter->ahw->diag_test) {
287*4882a593Smuzhiyun cap |= QLCNIC_CAP0_TX_MULTI;
288*4882a593Smuzhiyun } else {
289*4882a593Smuzhiyun temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
290*4882a593Smuzhiyun prq->valid_field_offset = cpu_to_le16(temp_u16);
291*4882a593Smuzhiyun prq->txrx_sds_binding = nsds_rings - 1;
292*4882a593Smuzhiyun temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
293*4882a593Smuzhiyun prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
294*4882a593Smuzhiyun temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
295*4882a593Smuzhiyun prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun prq->capabilities[0] = cpu_to_le32(cap);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun prq->num_rds_rings = cpu_to_le16(nrds_rings);
301*4882a593Smuzhiyun prq->num_sds_rings = cpu_to_le16(nsds_rings);
302*4882a593Smuzhiyun prq->rds_ring_offset = 0;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun val = le32_to_cpu(prq->rds_ring_offset) +
305*4882a593Smuzhiyun (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
306*4882a593Smuzhiyun prq->sds_ring_offset = cpu_to_le32(val);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
309*4882a593Smuzhiyun le32_to_cpu(prq->rds_ring_offset));
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun for (i = 0; i < nrds_rings; i++) {
312*4882a593Smuzhiyun rds_ring = &recv_ctx->rds_rings[i];
313*4882a593Smuzhiyun rds_ring->producer = 0;
314*4882a593Smuzhiyun prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
315*4882a593Smuzhiyun prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
316*4882a593Smuzhiyun prq_rds[i].ring_kind = cpu_to_le32(i);
317*4882a593Smuzhiyun prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
321*4882a593Smuzhiyun le32_to_cpu(prq->sds_ring_offset));
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun for (i = 0; i < nsds_rings; i++) {
324*4882a593Smuzhiyun sds_ring = &recv_ctx->sds_rings[i];
325*4882a593Smuzhiyun sds_ring->consumer = 0;
326*4882a593Smuzhiyun memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
327*4882a593Smuzhiyun prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
328*4882a593Smuzhiyun prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
329*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) &&
330*4882a593Smuzhiyun !adapter->ahw->diag_test)
331*4882a593Smuzhiyun prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
332*4882a593Smuzhiyun else
333*4882a593Smuzhiyun prq_sds[i].msi_index = cpu_to_le16(i);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun phys_addr = hostrq_phys_addr;
337*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
338*4882a593Smuzhiyun if (err)
339*4882a593Smuzhiyun goto out_free_rsp;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun cmd.req.arg[1] = MSD(phys_addr);
342*4882a593Smuzhiyun cmd.req.arg[2] = LSD(phys_addr);
343*4882a593Smuzhiyun cmd.req.arg[3] = rq_size;
344*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
345*4882a593Smuzhiyun if (err) {
346*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
347*4882a593Smuzhiyun "Failed to create rx ctx in firmware%d\n", err);
348*4882a593Smuzhiyun goto out_free_rsp;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
352*4882a593Smuzhiyun &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
355*4882a593Smuzhiyun rds_ring = &recv_ctx->rds_rings[i];
356*4882a593Smuzhiyun reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
357*4882a593Smuzhiyun rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
361*4882a593Smuzhiyun &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
364*4882a593Smuzhiyun sds_ring = &recv_ctx->sds_rings[i];
365*4882a593Smuzhiyun reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
366*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
367*4882a593Smuzhiyun reg2 = ahw->intr_tbl[i].src;
368*4882a593Smuzhiyun else
369*4882a593Smuzhiyun reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
372*4882a593Smuzhiyun sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
376*4882a593Smuzhiyun recv_ctx->context_id = le16_to_cpu(prsp->context_id);
377*4882a593Smuzhiyun recv_ctx->virt_port = prsp->virt_port;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
380*4882a593Smuzhiyun recv_ctx->context_id, recv_ctx->state);
381*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun out_free_rsp:
384*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
385*4882a593Smuzhiyun cardrsp_phys_addr);
386*4882a593Smuzhiyun out_free_rq:
387*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return err;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter * adapter)392*4882a593Smuzhiyun void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun int err;
395*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
396*4882a593Smuzhiyun struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
399*4882a593Smuzhiyun if (err)
400*4882a593Smuzhiyun return;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun cmd.req.arg[1] = recv_ctx->context_id;
403*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
404*4882a593Smuzhiyun if (err)
405*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
406*4882a593Smuzhiyun "Failed to destroy rx ctx in firmware\n");
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
409*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring,int ring)412*4882a593Smuzhiyun int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
413*4882a593Smuzhiyun struct qlcnic_host_tx_ring *tx_ring,
414*4882a593Smuzhiyun int ring)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
417*4882a593Smuzhiyun struct net_device *netdev = adapter->netdev;
418*4882a593Smuzhiyun struct qlcnic_hostrq_tx_ctx *prq;
419*4882a593Smuzhiyun struct qlcnic_hostrq_cds_ring *prq_cds;
420*4882a593Smuzhiyun struct qlcnic_cardrsp_tx_ctx *prsp;
421*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
422*4882a593Smuzhiyun u32 temp, intr_mask, temp_int_crb_mode;
423*4882a593Smuzhiyun dma_addr_t rq_phys_addr, rsp_phys_addr;
424*4882a593Smuzhiyun int temp_nsds_rings, index, err;
425*4882a593Smuzhiyun void *rq_addr, *rsp_addr;
426*4882a593Smuzhiyun size_t rq_size, rsp_size;
427*4882a593Smuzhiyun u64 phys_addr;
428*4882a593Smuzhiyun u16 msix_id;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /* reset host resources */
431*4882a593Smuzhiyun tx_ring->producer = 0;
432*4882a593Smuzhiyun tx_ring->sw_consumer = 0;
433*4882a593Smuzhiyun *(tx_ring->hw_consumer) = 0;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
436*4882a593Smuzhiyun rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
437*4882a593Smuzhiyun &rq_phys_addr, GFP_KERNEL);
438*4882a593Smuzhiyun if (!rq_addr)
439*4882a593Smuzhiyun return -ENOMEM;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
442*4882a593Smuzhiyun rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
443*4882a593Smuzhiyun &rsp_phys_addr, GFP_KERNEL);
444*4882a593Smuzhiyun if (!rsp_addr) {
445*4882a593Smuzhiyun err = -ENOMEM;
446*4882a593Smuzhiyun goto out_free_rq;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun prq = rq_addr;
450*4882a593Smuzhiyun prsp = rsp_addr;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
455*4882a593Smuzhiyun QLCNIC_CAP0_LSO);
456*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
457*4882a593Smuzhiyun temp |= QLCNIC_CAP0_TX_MULTI;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun prq->capabilities[0] = cpu_to_le32(temp);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) &&
462*4882a593Smuzhiyun !adapter->ahw->diag_test) {
463*4882a593Smuzhiyun temp_nsds_rings = adapter->drv_sds_rings;
464*4882a593Smuzhiyun index = temp_nsds_rings + ring;
465*4882a593Smuzhiyun msix_id = ahw->intr_tbl[index].id;
466*4882a593Smuzhiyun prq->msi_index = cpu_to_le16(msix_id);
467*4882a593Smuzhiyun } else {
468*4882a593Smuzhiyun temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
469*4882a593Smuzhiyun prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
470*4882a593Smuzhiyun prq->msi_index = 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun prq->interrupt_ctl = 0;
474*4882a593Smuzhiyun prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun prq_cds = &prq->cds_ring;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
479*4882a593Smuzhiyun prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun phys_addr = rq_phys_addr;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
484*4882a593Smuzhiyun if (err)
485*4882a593Smuzhiyun goto out_free_rsp;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun cmd.req.arg[1] = MSD(phys_addr);
488*4882a593Smuzhiyun cmd.req.arg[2] = LSD(phys_addr);
489*4882a593Smuzhiyun cmd.req.arg[3] = rq_size;
490*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun if (err == QLCNIC_RCODE_SUCCESS) {
493*4882a593Smuzhiyun tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
494*4882a593Smuzhiyun temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
495*4882a593Smuzhiyun tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
496*4882a593Smuzhiyun tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
497*4882a593Smuzhiyun if (qlcnic_check_multi_tx(adapter) &&
498*4882a593Smuzhiyun !adapter->ahw->diag_test &&
499*4882a593Smuzhiyun (adapter->flags & QLCNIC_MSIX_ENABLED)) {
500*4882a593Smuzhiyun index = adapter->drv_sds_rings + ring;
501*4882a593Smuzhiyun intr_mask = ahw->intr_tbl[index].src;
502*4882a593Smuzhiyun tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
506*4882a593Smuzhiyun tx_ring->ctx_id, tx_ring->state);
507*4882a593Smuzhiyun } else {
508*4882a593Smuzhiyun netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
509*4882a593Smuzhiyun err);
510*4882a593Smuzhiyun err = -EIO;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun out_free_rsp:
515*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
516*4882a593Smuzhiyun rsp_phys_addr);
517*4882a593Smuzhiyun out_free_rq:
518*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun return err;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)523*4882a593Smuzhiyun void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
524*4882a593Smuzhiyun struct qlcnic_host_tx_ring *tx_ring)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
527*4882a593Smuzhiyun int ret;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
530*4882a593Smuzhiyun if (ret)
531*4882a593Smuzhiyun return;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun cmd.req.arg[1] = tx_ring->ctx_id;
534*4882a593Smuzhiyun if (qlcnic_issue_cmd(adapter, &cmd))
535*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
536*4882a593Smuzhiyun "Failed to destroy tx ctx in firmware\n");
537*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun int
qlcnic_fw_cmd_set_port(struct qlcnic_adapter * adapter,u32 config)541*4882a593Smuzhiyun qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun int err;
544*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
547*4882a593Smuzhiyun if (err)
548*4882a593Smuzhiyun return err;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun cmd.req.arg[1] = config;
551*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
552*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
553*4882a593Smuzhiyun return err;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
qlcnic_alloc_hw_resources(struct qlcnic_adapter * adapter)556*4882a593Smuzhiyun int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun void *addr;
559*4882a593Smuzhiyun int err, ring;
560*4882a593Smuzhiyun struct qlcnic_recv_context *recv_ctx;
561*4882a593Smuzhiyun struct qlcnic_host_rds_ring *rds_ring;
562*4882a593Smuzhiyun struct qlcnic_host_sds_ring *sds_ring;
563*4882a593Smuzhiyun struct qlcnic_host_tx_ring *tx_ring;
564*4882a593Smuzhiyun __le32 *ptr;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun struct pci_dev *pdev = adapter->pdev;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun recv_ctx = adapter->recv_ctx;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
571*4882a593Smuzhiyun tx_ring = &adapter->tx_ring[ring];
572*4882a593Smuzhiyun ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
573*4882a593Smuzhiyun &tx_ring->hw_cons_phys_addr,
574*4882a593Smuzhiyun GFP_KERNEL);
575*4882a593Smuzhiyun if (ptr == NULL) {
576*4882a593Smuzhiyun err = -ENOMEM;
577*4882a593Smuzhiyun goto err_out_free;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun tx_ring->hw_consumer = ptr;
581*4882a593Smuzhiyun /* cmd desc ring */
582*4882a593Smuzhiyun addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
583*4882a593Smuzhiyun &tx_ring->phys_addr,
584*4882a593Smuzhiyun GFP_KERNEL);
585*4882a593Smuzhiyun if (addr == NULL) {
586*4882a593Smuzhiyun err = -ENOMEM;
587*4882a593Smuzhiyun goto err_out_free;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun tx_ring->desc_head = addr;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun for (ring = 0; ring < adapter->max_rds_rings; ring++) {
594*4882a593Smuzhiyun rds_ring = &recv_ctx->rds_rings[ring];
595*4882a593Smuzhiyun addr = dma_alloc_coherent(&adapter->pdev->dev,
596*4882a593Smuzhiyun RCV_DESC_RINGSIZE(rds_ring),
597*4882a593Smuzhiyun &rds_ring->phys_addr, GFP_KERNEL);
598*4882a593Smuzhiyun if (addr == NULL) {
599*4882a593Smuzhiyun err = -ENOMEM;
600*4882a593Smuzhiyun goto err_out_free;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun rds_ring->desc_head = addr;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
607*4882a593Smuzhiyun sds_ring = &recv_ctx->sds_rings[ring];
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun addr = dma_alloc_coherent(&adapter->pdev->dev,
610*4882a593Smuzhiyun STATUS_DESC_RINGSIZE(sds_ring),
611*4882a593Smuzhiyun &sds_ring->phys_addr, GFP_KERNEL);
612*4882a593Smuzhiyun if (addr == NULL) {
613*4882a593Smuzhiyun err = -ENOMEM;
614*4882a593Smuzhiyun goto err_out_free;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun sds_ring->desc_head = addr;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun return 0;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun err_out_free:
622*4882a593Smuzhiyun qlcnic_free_hw_resources(adapter);
623*4882a593Smuzhiyun return err;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
qlcnic_fw_create_ctx(struct qlcnic_adapter * dev)626*4882a593Smuzhiyun int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun int i, err, ring;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun if (dev->flags & QLCNIC_NEED_FLR) {
631*4882a593Smuzhiyun pci_reset_function(dev->pdev);
632*4882a593Smuzhiyun dev->flags &= ~QLCNIC_NEED_FLR;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
636*4882a593Smuzhiyun if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
637*4882a593Smuzhiyun err = qlcnic_83xx_config_intrpt(dev, 1);
638*4882a593Smuzhiyun if (err)
639*4882a593Smuzhiyun return err;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
644*4882a593Smuzhiyun qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
645*4882a593Smuzhiyun err = qlcnic_82xx_mq_intrpt(dev, 1);
646*4882a593Smuzhiyun if (err)
647*4882a593Smuzhiyun return err;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun err = qlcnic_fw_cmd_create_rx_ctx(dev);
651*4882a593Smuzhiyun if (err)
652*4882a593Smuzhiyun goto err_out;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun for (ring = 0; ring < dev->drv_tx_rings; ring++) {
655*4882a593Smuzhiyun err = qlcnic_fw_cmd_create_tx_ctx(dev,
656*4882a593Smuzhiyun &dev->tx_ring[ring],
657*4882a593Smuzhiyun ring);
658*4882a593Smuzhiyun if (err) {
659*4882a593Smuzhiyun qlcnic_fw_cmd_del_rx_ctx(dev);
660*4882a593Smuzhiyun if (ring == 0)
661*4882a593Smuzhiyun goto err_out;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun for (i = 0; i < ring; i++)
664*4882a593Smuzhiyun qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun goto err_out;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun return 0;
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun err_out:
675*4882a593Smuzhiyun if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
676*4882a593Smuzhiyun qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
677*4882a593Smuzhiyun qlcnic_82xx_config_intrpt(dev, 0);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
680*4882a593Smuzhiyun if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
681*4882a593Smuzhiyun qlcnic_83xx_config_intrpt(dev, 0);
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun return err;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
qlcnic_fw_destroy_ctx(struct qlcnic_adapter * adapter)687*4882a593Smuzhiyun void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun int ring;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
692*4882a593Smuzhiyun qlcnic_fw_cmd_del_rx_ctx(adapter);
693*4882a593Smuzhiyun for (ring = 0; ring < adapter->drv_tx_rings; ring++)
694*4882a593Smuzhiyun qlcnic_fw_cmd_del_tx_ctx(adapter,
695*4882a593Smuzhiyun &adapter->tx_ring[ring]);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun if (qlcnic_82xx_check(adapter) &&
698*4882a593Smuzhiyun (adapter->flags & QLCNIC_MSIX_ENABLED) &&
699*4882a593Smuzhiyun qlcnic_check_multi_tx(adapter) &&
700*4882a593Smuzhiyun !adapter->ahw->diag_test)
701*4882a593Smuzhiyun qlcnic_82xx_config_intrpt(adapter, 0);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun if (qlcnic_83xx_check(adapter) &&
704*4882a593Smuzhiyun (adapter->flags & QLCNIC_MSIX_ENABLED)) {
705*4882a593Smuzhiyun if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
706*4882a593Smuzhiyun qlcnic_83xx_config_intrpt(adapter, 0);
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun /* Allow dma queues to drain after context reset */
709*4882a593Smuzhiyun mdelay(20);
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
qlcnic_free_hw_resources(struct qlcnic_adapter * adapter)713*4882a593Smuzhiyun void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun struct qlcnic_recv_context *recv_ctx;
716*4882a593Smuzhiyun struct qlcnic_host_rds_ring *rds_ring;
717*4882a593Smuzhiyun struct qlcnic_host_sds_ring *sds_ring;
718*4882a593Smuzhiyun struct qlcnic_host_tx_ring *tx_ring;
719*4882a593Smuzhiyun int ring;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun recv_ctx = adapter->recv_ctx;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
724*4882a593Smuzhiyun tx_ring = &adapter->tx_ring[ring];
725*4882a593Smuzhiyun if (tx_ring->hw_consumer != NULL) {
726*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
727*4882a593Smuzhiyun tx_ring->hw_consumer,
728*4882a593Smuzhiyun tx_ring->hw_cons_phys_addr);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun tx_ring->hw_consumer = NULL;
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun if (tx_ring->desc_head != NULL) {
734*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev,
735*4882a593Smuzhiyun TX_DESC_RINGSIZE(tx_ring),
736*4882a593Smuzhiyun tx_ring->desc_head,
737*4882a593Smuzhiyun tx_ring->phys_addr);
738*4882a593Smuzhiyun tx_ring->desc_head = NULL;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun for (ring = 0; ring < adapter->max_rds_rings; ring++) {
743*4882a593Smuzhiyun rds_ring = &recv_ctx->rds_rings[ring];
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun if (rds_ring->desc_head != NULL) {
746*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev,
747*4882a593Smuzhiyun RCV_DESC_RINGSIZE(rds_ring),
748*4882a593Smuzhiyun rds_ring->desc_head,
749*4882a593Smuzhiyun rds_ring->phys_addr);
750*4882a593Smuzhiyun rds_ring->desc_head = NULL;
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
755*4882a593Smuzhiyun sds_ring = &recv_ctx->sds_rings[ring];
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun if (sds_ring->desc_head != NULL) {
758*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev,
759*4882a593Smuzhiyun STATUS_DESC_RINGSIZE(sds_ring),
760*4882a593Smuzhiyun sds_ring->desc_head,
761*4882a593Smuzhiyun sds_ring->phys_addr);
762*4882a593Smuzhiyun sds_ring->desc_head = NULL;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
qlcnic_82xx_config_intrpt(struct qlcnic_adapter * adapter,u8 op_type)767*4882a593Smuzhiyun int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
770*4882a593Smuzhiyun struct net_device *netdev = adapter->netdev;
771*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
772*4882a593Smuzhiyun u32 type, val;
773*4882a593Smuzhiyun int i, err = 0;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun for (i = 0; i < ahw->num_msix; i++) {
776*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
777*4882a593Smuzhiyun QLCNIC_CMD_MQ_TX_CONFIG_INTR);
778*4882a593Smuzhiyun if (err)
779*4882a593Smuzhiyun return err;
780*4882a593Smuzhiyun type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
781*4882a593Smuzhiyun val = type | (ahw->intr_tbl[i].type << 4);
782*4882a593Smuzhiyun if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
783*4882a593Smuzhiyun val |= (ahw->intr_tbl[i].id << 16);
784*4882a593Smuzhiyun cmd.req.arg[1] = val;
785*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
786*4882a593Smuzhiyun if (err) {
787*4882a593Smuzhiyun netdev_err(netdev, "Failed to %s interrupts %d\n",
788*4882a593Smuzhiyun op_type == QLCNIC_INTRPT_ADD ? "Add" :
789*4882a593Smuzhiyun "Delete", err);
790*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
791*4882a593Smuzhiyun return err;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun val = cmd.rsp.arg[1];
794*4882a593Smuzhiyun if (LSB(val)) {
795*4882a593Smuzhiyun netdev_info(netdev,
796*4882a593Smuzhiyun "failed to configure interrupt for %d\n",
797*4882a593Smuzhiyun ahw->intr_tbl[i].id);
798*4882a593Smuzhiyun continue;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun if (op_type) {
801*4882a593Smuzhiyun ahw->intr_tbl[i].id = MSW(val);
802*4882a593Smuzhiyun ahw->intr_tbl[i].enabled = 1;
803*4882a593Smuzhiyun ahw->intr_tbl[i].src = cmd.rsp.arg[2];
804*4882a593Smuzhiyun } else {
805*4882a593Smuzhiyun ahw->intr_tbl[i].id = i;
806*4882a593Smuzhiyun ahw->intr_tbl[i].enabled = 0;
807*4882a593Smuzhiyun ahw->intr_tbl[i].src = 0;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun return err;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
qlcnic_82xx_get_mac_address(struct qlcnic_adapter * adapter,u8 * mac,u8 function)815*4882a593Smuzhiyun int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
816*4882a593Smuzhiyun u8 function)
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun int err, i;
819*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
820*4882a593Smuzhiyun u32 mac_low, mac_high;
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
823*4882a593Smuzhiyun if (err)
824*4882a593Smuzhiyun return err;
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun cmd.req.arg[1] = function | BIT_8;
827*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun if (err == QLCNIC_RCODE_SUCCESS) {
830*4882a593Smuzhiyun mac_low = cmd.rsp.arg[1];
831*4882a593Smuzhiyun mac_high = cmd.rsp.arg[2];
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun for (i = 0; i < 2; i++)
834*4882a593Smuzhiyun mac[i] = (u8) (mac_high >> ((1 - i) * 8));
835*4882a593Smuzhiyun for (i = 2; i < 6; i++)
836*4882a593Smuzhiyun mac[i] = (u8) (mac_low >> ((5 - i) * 8));
837*4882a593Smuzhiyun } else {
838*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
839*4882a593Smuzhiyun "Failed to get mac address%d\n", err);
840*4882a593Smuzhiyun err = -EIO;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
843*4882a593Smuzhiyun return err;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun /* Get info of a NIC partition */
qlcnic_82xx_get_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * npar_info,u8 func_id)847*4882a593Smuzhiyun int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
848*4882a593Smuzhiyun struct qlcnic_info *npar_info, u8 func_id)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun int err;
851*4882a593Smuzhiyun dma_addr_t nic_dma_t;
852*4882a593Smuzhiyun const struct qlcnic_info_le *nic_info;
853*4882a593Smuzhiyun void *nic_info_addr;
854*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
855*4882a593Smuzhiyun size_t nic_size = sizeof(struct qlcnic_info_le);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
858*4882a593Smuzhiyun &nic_dma_t, GFP_KERNEL);
859*4882a593Smuzhiyun if (!nic_info_addr)
860*4882a593Smuzhiyun return -ENOMEM;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun nic_info = nic_info_addr;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
865*4882a593Smuzhiyun if (err)
866*4882a593Smuzhiyun goto out_free_dma;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun cmd.req.arg[1] = MSD(nic_dma_t);
869*4882a593Smuzhiyun cmd.req.arg[2] = LSD(nic_dma_t);
870*4882a593Smuzhiyun cmd.req.arg[3] = (func_id << 16 | nic_size);
871*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
872*4882a593Smuzhiyun if (err != QLCNIC_RCODE_SUCCESS) {
873*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
874*4882a593Smuzhiyun "Failed to get nic info%d\n", err);
875*4882a593Smuzhiyun err = -EIO;
876*4882a593Smuzhiyun } else {
877*4882a593Smuzhiyun npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
878*4882a593Smuzhiyun npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
879*4882a593Smuzhiyun npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
880*4882a593Smuzhiyun npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
881*4882a593Smuzhiyun npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
882*4882a593Smuzhiyun npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
883*4882a593Smuzhiyun npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
884*4882a593Smuzhiyun npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
885*4882a593Smuzhiyun npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
886*4882a593Smuzhiyun npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
890*4882a593Smuzhiyun out_free_dma:
891*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
892*4882a593Smuzhiyun nic_dma_t);
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun return err;
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun /* Configure a NIC partition */
qlcnic_82xx_set_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * nic)898*4882a593Smuzhiyun int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
899*4882a593Smuzhiyun struct qlcnic_info *nic)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun int err = -EIO;
902*4882a593Smuzhiyun dma_addr_t nic_dma_t;
903*4882a593Smuzhiyun void *nic_info_addr;
904*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
905*4882a593Smuzhiyun struct qlcnic_info_le *nic_info;
906*4882a593Smuzhiyun size_t nic_size = sizeof(struct qlcnic_info_le);
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
909*4882a593Smuzhiyun return err;
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
912*4882a593Smuzhiyun &nic_dma_t, GFP_KERNEL);
913*4882a593Smuzhiyun if (!nic_info_addr)
914*4882a593Smuzhiyun return -ENOMEM;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun nic_info = nic_info_addr;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun nic_info->pci_func = cpu_to_le16(nic->pci_func);
919*4882a593Smuzhiyun nic_info->op_mode = cpu_to_le16(nic->op_mode);
920*4882a593Smuzhiyun nic_info->phys_port = cpu_to_le16(nic->phys_port);
921*4882a593Smuzhiyun nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
922*4882a593Smuzhiyun nic_info->capabilities = cpu_to_le32(nic->capabilities);
923*4882a593Smuzhiyun nic_info->max_mac_filters = nic->max_mac_filters;
924*4882a593Smuzhiyun nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
925*4882a593Smuzhiyun nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
926*4882a593Smuzhiyun nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
927*4882a593Smuzhiyun nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
930*4882a593Smuzhiyun if (err)
931*4882a593Smuzhiyun goto out_free_dma;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun cmd.req.arg[1] = MSD(nic_dma_t);
934*4882a593Smuzhiyun cmd.req.arg[2] = LSD(nic_dma_t);
935*4882a593Smuzhiyun cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
936*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun if (err != QLCNIC_RCODE_SUCCESS) {
939*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
940*4882a593Smuzhiyun "Failed to set nic info%d\n", err);
941*4882a593Smuzhiyun err = -EIO;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
945*4882a593Smuzhiyun out_free_dma:
946*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
947*4882a593Smuzhiyun nic_dma_t);
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun return err;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun /* Get PCI Info of a partition */
qlcnic_82xx_get_pci_info(struct qlcnic_adapter * adapter,struct qlcnic_pci_info * pci_info)953*4882a593Smuzhiyun int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
954*4882a593Smuzhiyun struct qlcnic_pci_info *pci_info)
955*4882a593Smuzhiyun {
956*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
957*4882a593Smuzhiyun size_t npar_size = sizeof(struct qlcnic_pci_info_le);
958*4882a593Smuzhiyun size_t pci_size = npar_size * ahw->max_vnic_func;
959*4882a593Smuzhiyun u16 nic = 0, fcoe = 0, iscsi = 0;
960*4882a593Smuzhiyun struct qlcnic_pci_info_le *npar;
961*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
962*4882a593Smuzhiyun dma_addr_t pci_info_dma_t;
963*4882a593Smuzhiyun void *pci_info_addr;
964*4882a593Smuzhiyun int err = 0, i;
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
967*4882a593Smuzhiyun &pci_info_dma_t, GFP_KERNEL);
968*4882a593Smuzhiyun if (!pci_info_addr)
969*4882a593Smuzhiyun return -ENOMEM;
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun npar = pci_info_addr;
972*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
973*4882a593Smuzhiyun if (err)
974*4882a593Smuzhiyun goto out_free_dma;
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun cmd.req.arg[1] = MSD(pci_info_dma_t);
977*4882a593Smuzhiyun cmd.req.arg[2] = LSD(pci_info_dma_t);
978*4882a593Smuzhiyun cmd.req.arg[3] = pci_size;
979*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun ahw->total_nic_func = 0;
982*4882a593Smuzhiyun if (err == QLCNIC_RCODE_SUCCESS) {
983*4882a593Smuzhiyun for (i = 0; i < ahw->max_vnic_func; i++, npar++, pci_info++) {
984*4882a593Smuzhiyun pci_info->id = le16_to_cpu(npar->id);
985*4882a593Smuzhiyun pci_info->active = le16_to_cpu(npar->active);
986*4882a593Smuzhiyun if (!pci_info->active)
987*4882a593Smuzhiyun continue;
988*4882a593Smuzhiyun pci_info->type = le16_to_cpu(npar->type);
989*4882a593Smuzhiyun err = qlcnic_get_pci_func_type(adapter, pci_info->type,
990*4882a593Smuzhiyun &nic, &fcoe, &iscsi);
991*4882a593Smuzhiyun pci_info->default_port =
992*4882a593Smuzhiyun le16_to_cpu(npar->default_port);
993*4882a593Smuzhiyun pci_info->tx_min_bw =
994*4882a593Smuzhiyun le16_to_cpu(npar->tx_min_bw);
995*4882a593Smuzhiyun pci_info->tx_max_bw =
996*4882a593Smuzhiyun le16_to_cpu(npar->tx_max_bw);
997*4882a593Smuzhiyun memcpy(pci_info->mac, npar->mac, ETH_ALEN);
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun } else {
1000*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
1001*4882a593Smuzhiyun "Failed to get PCI Info%d\n", err);
1002*4882a593Smuzhiyun err = -EIO;
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun ahw->total_nic_func = nic;
1006*4882a593Smuzhiyun ahw->total_pci_func = nic + fcoe + iscsi;
1007*4882a593Smuzhiyun if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
1008*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
1009*4882a593Smuzhiyun "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
1010*4882a593Smuzhiyun __func__, ahw->total_nic_func, ahw->total_pci_func);
1011*4882a593Smuzhiyun err = -EIO;
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1014*4882a593Smuzhiyun out_free_dma:
1015*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
1016*4882a593Smuzhiyun pci_info_dma_t);
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun return err;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun /* Configure eSwitch for port mirroring */
qlcnic_config_port_mirroring(struct qlcnic_adapter * adapter,u8 id,u8 enable_mirroring,u8 pci_func)1022*4882a593Smuzhiyun int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
1023*4882a593Smuzhiyun u8 enable_mirroring, u8 pci_func)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun struct device *dev = &adapter->pdev->dev;
1026*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1027*4882a593Smuzhiyun int err = -EIO;
1028*4882a593Smuzhiyun u32 arg1;
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
1031*4882a593Smuzhiyun !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) {
1032*4882a593Smuzhiyun dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
1033*4882a593Smuzhiyun __func__);
1034*4882a593Smuzhiyun return err;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun arg1 = id | (enable_mirroring ? BIT_4 : 0);
1038*4882a593Smuzhiyun arg1 |= pci_func << 8;
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
1041*4882a593Smuzhiyun QLCNIC_CMD_SET_PORTMIRRORING);
1042*4882a593Smuzhiyun if (err)
1043*4882a593Smuzhiyun return err;
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun cmd.req.arg[1] = arg1;
1046*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun if (err != QLCNIC_RCODE_SUCCESS)
1049*4882a593Smuzhiyun dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
1050*4882a593Smuzhiyun pci_func, id);
1051*4882a593Smuzhiyun else
1052*4882a593Smuzhiyun dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
1053*4882a593Smuzhiyun pci_func, id);
1054*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun return err;
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun
qlcnic_get_port_stats(struct qlcnic_adapter * adapter,const u8 func,const u8 rx_tx,struct __qlcnic_esw_statistics * esw_stats)1059*4882a593Smuzhiyun int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
1060*4882a593Smuzhiyun const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
1063*4882a593Smuzhiyun struct qlcnic_esw_stats_le *stats;
1064*4882a593Smuzhiyun dma_addr_t stats_dma_t;
1065*4882a593Smuzhiyun void *stats_addr;
1066*4882a593Smuzhiyun u32 arg1;
1067*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1068*4882a593Smuzhiyun int err;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun if (esw_stats == NULL)
1071*4882a593Smuzhiyun return -ENOMEM;
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
1074*4882a593Smuzhiyun (func != adapter->ahw->pci_func)) {
1075*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
1076*4882a593Smuzhiyun "Not privilege to query stats for func=%d", func);
1077*4882a593Smuzhiyun return -EIO;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
1081*4882a593Smuzhiyun &stats_dma_t, GFP_KERNEL);
1082*4882a593Smuzhiyun if (!stats_addr)
1083*4882a593Smuzhiyun return -ENOMEM;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
1086*4882a593Smuzhiyun arg1 |= rx_tx << 15 | stats_size << 16;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
1089*4882a593Smuzhiyun QLCNIC_CMD_GET_ESWITCH_STATS);
1090*4882a593Smuzhiyun if (err)
1091*4882a593Smuzhiyun goto out_free_dma;
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun cmd.req.arg[1] = arg1;
1094*4882a593Smuzhiyun cmd.req.arg[2] = MSD(stats_dma_t);
1095*4882a593Smuzhiyun cmd.req.arg[3] = LSD(stats_dma_t);
1096*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun if (!err) {
1099*4882a593Smuzhiyun stats = stats_addr;
1100*4882a593Smuzhiyun esw_stats->context_id = le16_to_cpu(stats->context_id);
1101*4882a593Smuzhiyun esw_stats->version = le16_to_cpu(stats->version);
1102*4882a593Smuzhiyun esw_stats->size = le16_to_cpu(stats->size);
1103*4882a593Smuzhiyun esw_stats->multicast_frames =
1104*4882a593Smuzhiyun le64_to_cpu(stats->multicast_frames);
1105*4882a593Smuzhiyun esw_stats->broadcast_frames =
1106*4882a593Smuzhiyun le64_to_cpu(stats->broadcast_frames);
1107*4882a593Smuzhiyun esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
1108*4882a593Smuzhiyun esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
1109*4882a593Smuzhiyun esw_stats->local_frames = le64_to_cpu(stats->local_frames);
1110*4882a593Smuzhiyun esw_stats->errors = le64_to_cpu(stats->errors);
1111*4882a593Smuzhiyun esw_stats->numbytes = le64_to_cpu(stats->numbytes);
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1115*4882a593Smuzhiyun out_free_dma:
1116*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1117*4882a593Smuzhiyun stats_dma_t);
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun return err;
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun /* This routine will retrieve the MAC statistics from firmware */
qlcnic_get_mac_stats(struct qlcnic_adapter * adapter,struct qlcnic_mac_statistics * mac_stats)1123*4882a593Smuzhiyun int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
1124*4882a593Smuzhiyun struct qlcnic_mac_statistics *mac_stats)
1125*4882a593Smuzhiyun {
1126*4882a593Smuzhiyun struct qlcnic_mac_statistics_le *stats;
1127*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1128*4882a593Smuzhiyun size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
1129*4882a593Smuzhiyun dma_addr_t stats_dma_t;
1130*4882a593Smuzhiyun void *stats_addr;
1131*4882a593Smuzhiyun int err;
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun if (mac_stats == NULL)
1134*4882a593Smuzhiyun return -ENOMEM;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
1137*4882a593Smuzhiyun &stats_dma_t, GFP_KERNEL);
1138*4882a593Smuzhiyun if (!stats_addr)
1139*4882a593Smuzhiyun return -ENOMEM;
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
1142*4882a593Smuzhiyun if (err)
1143*4882a593Smuzhiyun goto out_free_dma;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun cmd.req.arg[1] = stats_size << 16;
1146*4882a593Smuzhiyun cmd.req.arg[2] = MSD(stats_dma_t);
1147*4882a593Smuzhiyun cmd.req.arg[3] = LSD(stats_dma_t);
1148*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1149*4882a593Smuzhiyun if (!err) {
1150*4882a593Smuzhiyun stats = stats_addr;
1151*4882a593Smuzhiyun mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
1152*4882a593Smuzhiyun mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
1153*4882a593Smuzhiyun mac_stats->mac_tx_mcast_pkts =
1154*4882a593Smuzhiyun le64_to_cpu(stats->mac_tx_mcast_pkts);
1155*4882a593Smuzhiyun mac_stats->mac_tx_bcast_pkts =
1156*4882a593Smuzhiyun le64_to_cpu(stats->mac_tx_bcast_pkts);
1157*4882a593Smuzhiyun mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
1158*4882a593Smuzhiyun mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
1159*4882a593Smuzhiyun mac_stats->mac_rx_mcast_pkts =
1160*4882a593Smuzhiyun le64_to_cpu(stats->mac_rx_mcast_pkts);
1161*4882a593Smuzhiyun mac_stats->mac_rx_length_error =
1162*4882a593Smuzhiyun le64_to_cpu(stats->mac_rx_length_error);
1163*4882a593Smuzhiyun mac_stats->mac_rx_length_small =
1164*4882a593Smuzhiyun le64_to_cpu(stats->mac_rx_length_small);
1165*4882a593Smuzhiyun mac_stats->mac_rx_length_large =
1166*4882a593Smuzhiyun le64_to_cpu(stats->mac_rx_length_large);
1167*4882a593Smuzhiyun mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
1168*4882a593Smuzhiyun mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
1169*4882a593Smuzhiyun mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
1170*4882a593Smuzhiyun } else {
1171*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
1172*4882a593Smuzhiyun "%s: Get mac stats failed, err=%d.\n", __func__, err);
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun out_free_dma:
1178*4882a593Smuzhiyun dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1179*4882a593Smuzhiyun stats_dma_t);
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun return err;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun
qlcnic_get_eswitch_stats(struct qlcnic_adapter * adapter,const u8 eswitch,const u8 rx_tx,struct __qlcnic_esw_statistics * esw_stats)1184*4882a593Smuzhiyun int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
1185*4882a593Smuzhiyun const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun struct __qlcnic_esw_statistics port_stats;
1188*4882a593Smuzhiyun u8 i;
1189*4882a593Smuzhiyun int ret = -EIO;
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun if (esw_stats == NULL)
1192*4882a593Smuzhiyun return -ENOMEM;
1193*4882a593Smuzhiyun if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
1194*4882a593Smuzhiyun return -EIO;
1195*4882a593Smuzhiyun if (adapter->npars == NULL)
1196*4882a593Smuzhiyun return -EIO;
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun memset(esw_stats, 0, sizeof(u64));
1199*4882a593Smuzhiyun esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
1200*4882a593Smuzhiyun esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
1201*4882a593Smuzhiyun esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
1202*4882a593Smuzhiyun esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
1203*4882a593Smuzhiyun esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
1204*4882a593Smuzhiyun esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
1205*4882a593Smuzhiyun esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
1206*4882a593Smuzhiyun esw_stats->context_id = eswitch;
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun for (i = 0; i < adapter->ahw->total_nic_func; i++) {
1209*4882a593Smuzhiyun if (adapter->npars[i].phy_port != eswitch)
1210*4882a593Smuzhiyun continue;
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
1213*4882a593Smuzhiyun if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
1214*4882a593Smuzhiyun rx_tx, &port_stats))
1215*4882a593Smuzhiyun continue;
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun esw_stats->size = port_stats.size;
1218*4882a593Smuzhiyun esw_stats->version = port_stats.version;
1219*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
1220*4882a593Smuzhiyun port_stats.unicast_frames);
1221*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
1222*4882a593Smuzhiyun port_stats.multicast_frames);
1223*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
1224*4882a593Smuzhiyun port_stats.broadcast_frames);
1225*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
1226*4882a593Smuzhiyun port_stats.dropped_frames);
1227*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->errors,
1228*4882a593Smuzhiyun port_stats.errors);
1229*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
1230*4882a593Smuzhiyun port_stats.local_frames);
1231*4882a593Smuzhiyun QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
1232*4882a593Smuzhiyun port_stats.numbytes);
1233*4882a593Smuzhiyun ret = 0;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun return ret;
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun
qlcnic_clear_esw_stats(struct qlcnic_adapter * adapter,const u8 func_esw,const u8 port,const u8 rx_tx)1238*4882a593Smuzhiyun int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
1239*4882a593Smuzhiyun const u8 port, const u8 rx_tx)
1240*4882a593Smuzhiyun {
1241*4882a593Smuzhiyun struct qlcnic_hardware_context *ahw = adapter->ahw;
1242*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1243*4882a593Smuzhiyun int err;
1244*4882a593Smuzhiyun u32 arg1;
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun if (ahw->op_mode != QLCNIC_MGMT_FUNC)
1247*4882a593Smuzhiyun return -EIO;
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun if (func_esw == QLCNIC_STATS_PORT) {
1250*4882a593Smuzhiyun if (port >= ahw->max_vnic_func)
1251*4882a593Smuzhiyun goto err_ret;
1252*4882a593Smuzhiyun } else if (func_esw == QLCNIC_STATS_ESWITCH) {
1253*4882a593Smuzhiyun if (port >= QLCNIC_NIU_MAX_XG_PORTS)
1254*4882a593Smuzhiyun goto err_ret;
1255*4882a593Smuzhiyun } else {
1256*4882a593Smuzhiyun goto err_ret;
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
1260*4882a593Smuzhiyun goto err_ret;
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
1263*4882a593Smuzhiyun arg1 |= BIT_14 | rx_tx << 15;
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
1266*4882a593Smuzhiyun QLCNIC_CMD_GET_ESWITCH_STATS);
1267*4882a593Smuzhiyun if (err)
1268*4882a593Smuzhiyun return err;
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun cmd.req.arg[1] = arg1;
1271*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1272*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1273*4882a593Smuzhiyun return err;
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun err_ret:
1276*4882a593Smuzhiyun dev_err(&adapter->pdev->dev,
1277*4882a593Smuzhiyun "Invalid args func_esw %d port %d rx_ctx %d\n",
1278*4882a593Smuzhiyun func_esw, port, rx_tx);
1279*4882a593Smuzhiyun return -EIO;
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
__qlcnic_get_eswitch_port_config(struct qlcnic_adapter * adapter,u32 * arg1,u32 * arg2)1282*4882a593Smuzhiyun static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1283*4882a593Smuzhiyun u32 *arg1, u32 *arg2)
1284*4882a593Smuzhiyun {
1285*4882a593Smuzhiyun struct device *dev = &adapter->pdev->dev;
1286*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1287*4882a593Smuzhiyun u8 pci_func = *arg1 >> 8;
1288*4882a593Smuzhiyun int err;
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
1291*4882a593Smuzhiyun QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
1292*4882a593Smuzhiyun if (err)
1293*4882a593Smuzhiyun return err;
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun cmd.req.arg[1] = *arg1;
1296*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1297*4882a593Smuzhiyun *arg1 = cmd.rsp.arg[1];
1298*4882a593Smuzhiyun *arg2 = cmd.rsp.arg[2];
1299*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun if (err == QLCNIC_RCODE_SUCCESS)
1302*4882a593Smuzhiyun dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
1303*4882a593Smuzhiyun pci_func);
1304*4882a593Smuzhiyun else
1305*4882a593Smuzhiyun dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
1306*4882a593Smuzhiyun pci_func);
1307*4882a593Smuzhiyun return err;
1308*4882a593Smuzhiyun }
1309*4882a593Smuzhiyun /* Configure eSwitch port
1310*4882a593Smuzhiyun op_mode = 0 for setting default port behavior
1311*4882a593Smuzhiyun op_mode = 1 for setting vlan id
1312*4882a593Smuzhiyun op_mode = 2 for deleting vlan id
1313*4882a593Smuzhiyun op_type = 0 for vlan_id
1314*4882a593Smuzhiyun op_type = 1 for port vlan_id
1315*4882a593Smuzhiyun */
qlcnic_config_switch_port(struct qlcnic_adapter * adapter,struct qlcnic_esw_func_cfg * esw_cfg)1316*4882a593Smuzhiyun int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
1317*4882a593Smuzhiyun struct qlcnic_esw_func_cfg *esw_cfg)
1318*4882a593Smuzhiyun {
1319*4882a593Smuzhiyun struct device *dev = &adapter->pdev->dev;
1320*4882a593Smuzhiyun struct qlcnic_cmd_args cmd;
1321*4882a593Smuzhiyun int err = -EIO, index;
1322*4882a593Smuzhiyun u32 arg1, arg2 = 0;
1323*4882a593Smuzhiyun u8 pci_func;
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1326*4882a593Smuzhiyun dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
1327*4882a593Smuzhiyun __func__);
1328*4882a593Smuzhiyun return err;
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun pci_func = esw_cfg->pci_func;
1332*4882a593Smuzhiyun index = qlcnic_is_valid_nic_func(adapter, pci_func);
1333*4882a593Smuzhiyun if (index < 0)
1334*4882a593Smuzhiyun return err;
1335*4882a593Smuzhiyun arg1 = (adapter->npars[index].phy_port & BIT_0);
1336*4882a593Smuzhiyun arg1 |= (pci_func << 8);
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1339*4882a593Smuzhiyun return err;
1340*4882a593Smuzhiyun arg1 &= ~(0x0ff << 8);
1341*4882a593Smuzhiyun arg1 |= (pci_func << 8);
1342*4882a593Smuzhiyun arg1 &= ~(BIT_2 | BIT_3);
1343*4882a593Smuzhiyun switch (esw_cfg->op_mode) {
1344*4882a593Smuzhiyun case QLCNIC_PORT_DEFAULTS:
1345*4882a593Smuzhiyun arg1 |= (BIT_4 | BIT_6 | BIT_7);
1346*4882a593Smuzhiyun arg2 |= (BIT_0 | BIT_1);
1347*4882a593Smuzhiyun if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1348*4882a593Smuzhiyun arg2 |= (BIT_2 | BIT_3);
1349*4882a593Smuzhiyun if (!(esw_cfg->discard_tagged))
1350*4882a593Smuzhiyun arg1 &= ~BIT_4;
1351*4882a593Smuzhiyun if (!(esw_cfg->promisc_mode))
1352*4882a593Smuzhiyun arg1 &= ~BIT_6;
1353*4882a593Smuzhiyun if (!(esw_cfg->mac_override))
1354*4882a593Smuzhiyun arg1 &= ~BIT_7;
1355*4882a593Smuzhiyun if (!(esw_cfg->mac_anti_spoof))
1356*4882a593Smuzhiyun arg2 &= ~BIT_0;
1357*4882a593Smuzhiyun if (!(esw_cfg->offload_flags & BIT_0))
1358*4882a593Smuzhiyun arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1359*4882a593Smuzhiyun if (!(esw_cfg->offload_flags & BIT_1))
1360*4882a593Smuzhiyun arg2 &= ~BIT_2;
1361*4882a593Smuzhiyun if (!(esw_cfg->offload_flags & BIT_2))
1362*4882a593Smuzhiyun arg2 &= ~BIT_3;
1363*4882a593Smuzhiyun break;
1364*4882a593Smuzhiyun case QLCNIC_ADD_VLAN:
1365*4882a593Smuzhiyun arg1 &= ~(0x0ffff << 16);
1366*4882a593Smuzhiyun arg1 |= (BIT_2 | BIT_5);
1367*4882a593Smuzhiyun arg1 |= (esw_cfg->vlan_id << 16);
1368*4882a593Smuzhiyun break;
1369*4882a593Smuzhiyun case QLCNIC_DEL_VLAN:
1370*4882a593Smuzhiyun arg1 |= (BIT_3 | BIT_5);
1371*4882a593Smuzhiyun arg1 &= ~(0x0ffff << 16);
1372*4882a593Smuzhiyun break;
1373*4882a593Smuzhiyun default:
1374*4882a593Smuzhiyun dev_err(&adapter->pdev->dev, "%s: Invalid opmode 0x%x\n",
1375*4882a593Smuzhiyun __func__, esw_cfg->op_mode);
1376*4882a593Smuzhiyun return err;
1377*4882a593Smuzhiyun }
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun err = qlcnic_alloc_mbx_args(&cmd, adapter,
1380*4882a593Smuzhiyun QLCNIC_CMD_CONFIGURE_ESWITCH);
1381*4882a593Smuzhiyun if (err)
1382*4882a593Smuzhiyun return err;
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun cmd.req.arg[1] = arg1;
1385*4882a593Smuzhiyun cmd.req.arg[2] = arg2;
1386*4882a593Smuzhiyun err = qlcnic_issue_cmd(adapter, &cmd);
1387*4882a593Smuzhiyun qlcnic_free_mbx_args(&cmd);
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun if (err != QLCNIC_RCODE_SUCCESS)
1390*4882a593Smuzhiyun dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
1391*4882a593Smuzhiyun pci_func);
1392*4882a593Smuzhiyun else
1393*4882a593Smuzhiyun dev_info(dev, "Configured eSwitch for vNIC function %d\n",
1394*4882a593Smuzhiyun pci_func);
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun return err;
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun int
qlcnic_get_eswitch_port_config(struct qlcnic_adapter * adapter,struct qlcnic_esw_func_cfg * esw_cfg)1400*4882a593Smuzhiyun qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1401*4882a593Smuzhiyun struct qlcnic_esw_func_cfg *esw_cfg)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun u32 arg1, arg2;
1404*4882a593Smuzhiyun int index;
1405*4882a593Smuzhiyun u8 phy_port;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
1408*4882a593Smuzhiyun index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
1409*4882a593Smuzhiyun if (index < 0)
1410*4882a593Smuzhiyun return -EIO;
1411*4882a593Smuzhiyun phy_port = adapter->npars[index].phy_port;
1412*4882a593Smuzhiyun } else {
1413*4882a593Smuzhiyun phy_port = adapter->ahw->physical_port;
1414*4882a593Smuzhiyun }
1415*4882a593Smuzhiyun arg1 = phy_port;
1416*4882a593Smuzhiyun arg1 |= (esw_cfg->pci_func << 8);
1417*4882a593Smuzhiyun if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1418*4882a593Smuzhiyun return -EIO;
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun esw_cfg->discard_tagged = !!(arg1 & BIT_4);
1421*4882a593Smuzhiyun esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
1422*4882a593Smuzhiyun esw_cfg->promisc_mode = !!(arg1 & BIT_6);
1423*4882a593Smuzhiyun esw_cfg->mac_override = !!(arg1 & BIT_7);
1424*4882a593Smuzhiyun esw_cfg->vlan_id = LSW(arg1 >> 16);
1425*4882a593Smuzhiyun esw_cfg->mac_anti_spoof = (arg2 & 0x1);
1426*4882a593Smuzhiyun esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun return 0;
1429*4882a593Smuzhiyun }
1430