xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/realtek/r8168/r8168_dash.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun ################################################################################
4*4882a593Smuzhiyun #
5*4882a593Smuzhiyun # r8168 is the Linux device driver released for Realtek Gigabit Ethernet
6*4882a593Smuzhiyun # controllers with PCI-Express interface.
7*4882a593Smuzhiyun #
8*4882a593Smuzhiyun # Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
9*4882a593Smuzhiyun #
10*4882a593Smuzhiyun # This program is free software; you can redistribute it and/or modify it
11*4882a593Smuzhiyun # under the terms of the GNU General Public License as published by the Free
12*4882a593Smuzhiyun # Software Foundation; either version 2 of the License, or (at your option)
13*4882a593Smuzhiyun # any later version.
14*4882a593Smuzhiyun #
15*4882a593Smuzhiyun # This program is distributed in the hope that it will be useful, but WITHOUT
16*4882a593Smuzhiyun # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17*4882a593Smuzhiyun # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18*4882a593Smuzhiyun # more details.
19*4882a593Smuzhiyun #
20*4882a593Smuzhiyun # You should have received a copy of the GNU General Public License along with
21*4882a593Smuzhiyun # this program; if not, see <http://www.gnu.org/licenses/>.
22*4882a593Smuzhiyun #
23*4882a593Smuzhiyun # Author:
24*4882a593Smuzhiyun # Realtek NIC software team <nicfae@realtek.com>
25*4882a593Smuzhiyun # No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
26*4882a593Smuzhiyun #
27*4882a593Smuzhiyun ################################################################################
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /************************************************************************************
31*4882a593Smuzhiyun  *  This product is covered by one or more of the following patents:
32*4882a593Smuzhiyun  *  US6,570,884, US6,115,776, and US6,327,625.
33*4882a593Smuzhiyun  ***********************************************************************************/
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifndef _LINUX_R8168_DASH_H
36*4882a593Smuzhiyun #define _LINUX_R8168_DASH_H
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define SIOCDEVPRIVATE_RTLDASH   SIOCDEVPRIVATE+2
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun enum rtl_dash_cmd {
41*4882a593Smuzhiyun         RTL_DASH_ARP_NS_OFFLOAD = 0,
42*4882a593Smuzhiyun         RTL_DASH_SET_OOB_IPMAC,
43*4882a593Smuzhiyun         RTL_DASH_NOTIFY_OOB,
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun         RTL_DASH_SEND_BUFFER_DATA_TO_DASH_FW,
46*4882a593Smuzhiyun         RTL_DASH_CHECK_SEND_BUFFER_TO_DASH_FW_COMPLETE,
47*4882a593Smuzhiyun         RTL_DASH_GET_RCV_FROM_FW_BUFFER_DATA,
48*4882a593Smuzhiyun         RTL_DASH_OOB_REQ,
49*4882a593Smuzhiyun         RTL_DASH_OOB_ACK,
50*4882a593Smuzhiyun         RTL_DASH_DETACH_OOB_REQ,
51*4882a593Smuzhiyun         RTL_DASH_DETACH_OOB_ACK,
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun         RTL_FW_SET_IPV4 = 0x10,
54*4882a593Smuzhiyun         RTL_FW_GET_IPV4,
55*4882a593Smuzhiyun         RTL_FW_SET_IPV6,
56*4882a593Smuzhiyun         RTL_FW_GET_IPV6,
57*4882a593Smuzhiyun         RTL_FW_SET_EXT_SNMP,
58*4882a593Smuzhiyun         RTL_FW_GET_EXT_SNMP,
59*4882a593Smuzhiyun         RTL_FW_SET_WAKEUP_PATTERN,
60*4882a593Smuzhiyun         RTL_FW_GET_WAKEUP_PATTERN,
61*4882a593Smuzhiyun         RTL_FW_DEL_WAKEUP_PATTERN,
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun         RTLT_DASH_COMMAND_INVALID,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun struct rtl_dash_ip_mac {
67*4882a593Smuzhiyun         struct sockaddr ifru_addr;
68*4882a593Smuzhiyun         struct sockaddr ifru_netmask;
69*4882a593Smuzhiyun         struct sockaddr ifru_hwaddr;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun struct rtl_dash_ioctl_struct {
73*4882a593Smuzhiyun         __u32	cmd;
74*4882a593Smuzhiyun         __u32	offset;
75*4882a593Smuzhiyun         __u32	len;
76*4882a593Smuzhiyun         union {
77*4882a593Smuzhiyun                 __u32	data;
78*4882a593Smuzhiyun                 void *data_buffer;
79*4882a593Smuzhiyun         };
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun struct settings_ipv4 {
83*4882a593Smuzhiyun         __u32	IPv4addr;
84*4882a593Smuzhiyun         __u32	IPv4mask;
85*4882a593Smuzhiyun         __u32	IPv4Gateway;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct settings_ipv6 {
89*4882a593Smuzhiyun         __u32	reserved;
90*4882a593Smuzhiyun         __u32	prefixLen;
91*4882a593Smuzhiyun         __u16	IPv6addr[8];
92*4882a593Smuzhiyun         __u16	IPv6Gateway[8];
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun struct settings_ext_snmp {
96*4882a593Smuzhiyun         __u16	index;
97*4882a593Smuzhiyun         __u16	oid_get_len;
98*4882a593Smuzhiyun         __u8	oid_for_get[24];
99*4882a593Smuzhiyun         __u8	reserved0[26];
100*4882a593Smuzhiyun         __u16	value_len;
101*4882a593Smuzhiyun         __u8	value[256];
102*4882a593Smuzhiyun         __u8	supported;
103*4882a593Smuzhiyun         __u8	reserved1[27];
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct wakeup_pattern {
107*4882a593Smuzhiyun         __u8	index;
108*4882a593Smuzhiyun         __u8	valid;
109*4882a593Smuzhiyun         __u8	start;
110*4882a593Smuzhiyun         __u8	length;
111*4882a593Smuzhiyun         __u8	name[36];
112*4882a593Smuzhiyun         __u8	mask[16];
113*4882a593Smuzhiyun         __u8	pattern[128];
114*4882a593Smuzhiyun         __u32	reserved[2];
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun typedef struct _RX_DASH_FROM_FW_DESC {
118*4882a593Smuzhiyun         __le16 length;
119*4882a593Smuzhiyun         __le16 status;
120*4882a593Smuzhiyun         __le32 resv;
121*4882a593Smuzhiyun         __le64 BufferAddress;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun RX_DASH_FROM_FW_DESC, *PRX_DASH_FROM_FW_DESC;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun typedef struct _TX_DASH_SEND_FW_DESC {
126*4882a593Smuzhiyun         __le16 length;
127*4882a593Smuzhiyun         __le16 status;
128*4882a593Smuzhiyun         __le32 resv;
129*4882a593Smuzhiyun         __le64 BufferAddress;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun TX_DASH_SEND_FW_DESC, *PTX_DASH_SEND_FW_DESC;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun typedef struct _OSOOBHdr {
134*4882a593Smuzhiyun         __le32 len;
135*4882a593Smuzhiyun         u8 type;
136*4882a593Smuzhiyun         u8 flag;
137*4882a593Smuzhiyun         u8 hostReqV;
138*4882a593Smuzhiyun         u8 res;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun OSOOBHdr, *POSOOBHdr;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun typedef struct _RX_DASH_BUFFER_TYPE_2 {
143*4882a593Smuzhiyun         OSOOBHdr oobhdr;
144*4882a593Smuzhiyun         u8 RxDataBuffer[0];
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define ALIGN_8                 (0x7)
149*4882a593Smuzhiyun #define ALIGN_16                (0xf)
150*4882a593Smuzhiyun #define ALIGN_32                (0x1f)
151*4882a593Smuzhiyun #define ALIGN_64                (0x3f)
152*4882a593Smuzhiyun #define ALIGN_256               (0xff)
153*4882a593Smuzhiyun #define ALIGN_4096              (0xfff)
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #define OCP_REG_CONFIG0 (0x10)
156*4882a593Smuzhiyun #define OCP_REG_CONFIG0_REV_F (0xB8)
157*4882a593Smuzhiyun #define OCP_REG_DASH_POLL (0x30)
158*4882a593Smuzhiyun #define OCP_REG_HOST_REQ (0x34)
159*4882a593Smuzhiyun #define OCP_REG_DASH_REQ (0x35)
160*4882a593Smuzhiyun #define OCP_REG_CR (0x36)
161*4882a593Smuzhiyun #define OCP_REG_DMEMSTA (0x38)
162*4882a593Smuzhiyun #define OCP_REG_GPHYAR (0x60)
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #define OCP_REG_CONFIG0_DASHEN           BIT_15
166*4882a593Smuzhiyun #define OCP_REG_CONFIG0_OOBRESET         BIT_14
167*4882a593Smuzhiyun #define OCP_REG_CONFIG0_APRDY            BIT_13
168*4882a593Smuzhiyun #define OCP_REG_CONFIG0_FIRMWARERDY      BIT_12
169*4882a593Smuzhiyun #define OCP_REG_CONFIG0_DRIVERRDY        BIT_11
170*4882a593Smuzhiyun #define OCP_REG_CONFIG0_OOB_WDT          BIT_9
171*4882a593Smuzhiyun #define OCP_REG_CONFIG0_DRV_WAIT_OOB     BIT_8
172*4882a593Smuzhiyun #define OCP_REG_CONFIG0_TLSEN            BIT_7
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define HW_DASH_SUPPORT_DASH(_M)        ((_M)->HwSuppDashVer > 0)
175*4882a593Smuzhiyun #define HW_DASH_SUPPORT_TYPE_1(_M)        ((_M)->HwSuppDashVer == 1)
176*4882a593Smuzhiyun #define HW_DASH_SUPPORT_TYPE_2(_M)        ((_M)->HwSuppDashVer == 2)
177*4882a593Smuzhiyun #define HW_DASH_SUPPORT_TYPE_3(_M)        ((_M)->HwSuppDashVer == 3)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #define RECV_FROM_FW_BUF_SIZE (2048)
180*4882a593Smuzhiyun #define SEND_TO_FW_BUF_SIZE (2048)
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define RX_DASH_FROM_FW_OWN BIT_15
183*4882a593Smuzhiyun #define TX_DASH_SEND_FW_OWN BIT_15
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun #define TXS_CC3_0       (BIT_0|BIT_1|BIT_2|BIT_3)
186*4882a593Smuzhiyun #define TXS_EXC         BIT_4
187*4882a593Smuzhiyun #define TXS_LNKF        BIT_5
188*4882a593Smuzhiyun #define TXS_OWC         BIT_6
189*4882a593Smuzhiyun #define TXS_TES         BIT_7
190*4882a593Smuzhiyun #define TXS_UNF         BIT_9
191*4882a593Smuzhiyun #define TXS_LGSEN       BIT_11
192*4882a593Smuzhiyun #define TXS_LS          BIT_12
193*4882a593Smuzhiyun #define TXS_FS          BIT_13
194*4882a593Smuzhiyun #define TXS_EOR         BIT_14
195*4882a593Smuzhiyun #define TXS_OWN         BIT_15
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun #define TPPool_HRDY     0x20
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun #define HostReqReg (0xC0)
200*4882a593Smuzhiyun #define SystemMasterDescStartAddrLow (0xF0)
201*4882a593Smuzhiyun #define SystemMasterDescStartAddrHigh (0xF4)
202*4882a593Smuzhiyun #define SystemSlaveDescStartAddrLow (0xF8)
203*4882a593Smuzhiyun #define SystemSlaveDescStartAddrHigh (0xFC)
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun //DASH Request Type
206*4882a593Smuzhiyun #define WSMANREG 0x01
207*4882a593Smuzhiyun #define OSPUSHDATA 0x02
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun #define RXS_OWN      BIT_15
210*4882a593Smuzhiyun #define RXS_EOR      BIT_14
211*4882a593Smuzhiyun #define RXS_FS       BIT_13
212*4882a593Smuzhiyun #define RXS_LS       BIT_12
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #define ISRIMR_DP_DASH_OK BIT_15
215*4882a593Smuzhiyun #define ISRIMR_DP_HOST_OK BIT_13
216*4882a593Smuzhiyun #define ISRIMR_DP_REQSYS_OK BIT_11
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun #define ISRIMR_DASH_INTR_EN BIT_12
219*4882a593Smuzhiyun #define ISRIMR_DASH_INTR_CMAC_RESET BIT_15
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_ROK BIT_0
222*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_RDU BIT_1
223*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_TOK BIT_2
224*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_TDU BIT_3
225*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_TX_FIFO_FULL BIT_4
226*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5
227*4882a593Smuzhiyun #define ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE BIT_6
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun #define CMAC_OOB_STOP 0x25
230*4882a593Smuzhiyun #define CMAC_OOB_INIT 0x26
231*4882a593Smuzhiyun #define CMAC_OOB_RESET 0x2a
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun #define NO_BASE_ADDRESS 0x00000000
234*4882a593Smuzhiyun #define RTL8168FP_OOBMAC_BASE 0xBAF70000
235*4882a593Smuzhiyun #define RTL8168FP_CMAC_IOBASE 0xBAF20000
236*4882a593Smuzhiyun #define RTL8168FP_KVM_BASE 0xBAF80400
237*4882a593Smuzhiyun #define CMAC_SYNC_REG 0x20
238*4882a593Smuzhiyun #define CMAC_RXDESC_OFFSET 0x90    //RX: 0x90 - 0x98
239*4882a593Smuzhiyun #define CMAC_TXDESC_OFFSET 0x98    //TX: 0x98 - 0x9F
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun /* cmac write/read MMIO register */
242*4882a593Smuzhiyun #define RTL_CMAC_W8(tp, reg, val8)   writeb ((val8), tp->cmac_ioaddr + (reg))
243*4882a593Smuzhiyun #define RTL_CMAC_W16(tp, reg, val16) writew ((val16), tp->cmac_ioaddr + (reg))
244*4882a593Smuzhiyun #define RTL_CMAC_W32(tp, reg, val32) writel ((val32), tp->cmac_ioaddr + (reg))
245*4882a593Smuzhiyun #define RTL_CMAC_R8(tp, reg)     readb (tp->cmac_ioaddr + (reg))
246*4882a593Smuzhiyun #define RTL_CMAC_R16(tp, reg)        readw (tp->cmac_ioaddr + (reg))
247*4882a593Smuzhiyun #define RTL_CMAC_R32(tp, reg)        ((unsigned long) readl (tp->cmac_ioaddr + (reg)))
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun int rtl8168_dash_ioctl(struct net_device *dev, struct ifreq *ifr);
250*4882a593Smuzhiyun void HandleDashInterrupt(struct net_device *dev);
251*4882a593Smuzhiyun int AllocateDashShareMemory(struct net_device *dev);
252*4882a593Smuzhiyun void FreeAllocatedDashShareMemory(struct net_device *dev);
253*4882a593Smuzhiyun void DashHwInit(struct net_device *dev);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun #endif /* _LINUX_R8168_DASH_H */
257