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Searched +full:rk3066 +full:- +full:smp +full:- +full:sram (Results 1 – 25 of 27) sorted by relevance

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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/smp.h>
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3066a.dtsi5 * SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3066a-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A Drk3188.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A D.rk3066a-mk808.dtb.dts.tmp
H A D.rk3188-radxarock.dtb.dts.tmp
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
[all …]
H A Drk3036.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3036-cru.h>
15 interrupt-parent = <&gic>;
34 arm-pmu {
35 compatible = "arm,cortex-a7-pmu";
38 interrupt-affinity = <&cpu0>, <&cpu1>;
[all …]
H A Drk322x.dtsi4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3228-cru.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
[all …]
H A D.rk3288-vyasa.dtb.dts.tmp
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3036-sdk.dtb.dts.tmp
H A D.rk3288-popmetal.dtb.dts.tmp
H A D.rk3288-tinker.dtb.dts.tmp
H A D.rk3288-evb.dtb.dts.tmp
H A D.rk3288-fennec.dtb.dts.tmp
H A D.rk3288-firefly.dtb.dts.tmp
H A D.rk3288-miqi.dtb.dts.tmp
H A D.rk3288-phycore-rdk.dtb.dts.tmp
H A D.rk3288-veyron-mickey.dtb.dts.tmp
H A D.rk3288-veyron-minnie.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "rockchip,rk3066-smp";
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/power/rk3036-power.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/suspend/rockchip-rk3288.h>
[all …]

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