1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 mmc0 = &emmc; 25 mmc1 = &sdmmc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 clock-latency = <40000>; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 amba { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 pdma: pdma@110f0000 { 75 compatible = "arm,pl330", "arm,primecell"; 76 reg = <0x110f0000 0x4000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 arm-pmu { 86 compatible = "arm,cortex-a7-pmu"; 87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 92 }; 93 94 memory@60000000 { 95 device_type = "memory"; 96 reg = <0x60000000 0x40000000>; 97 }; 98 99 psci: psci { 100 compatible = "arm,psci-1.0"; 101 method = "smc"; 102 }; 103 104 timer { 105 compatible = "arm,armv7-timer"; 106 arm,cpu-registers-not-fw-configured; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111 clock-frequency = <24000000>; 112 }; 113 114 xin24m: oscillator { 115 compatible = "fixed-clock"; 116 clock-frequency = <24000000>; 117 clock-output-names = "xin24m"; 118 #clock-cells = <0>; 119 }; 120 121 bus_intmem@10080000 { 122 compatible = "mmio-sram"; 123 reg = <0x10080000 0x9000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0x10080000 0x9000>; 127 smp-sram@0 { 128 compatible = "rockchip,rk322x-smp-sram"; 129 reg = <0x00 0x10>; 130 }; 131 ddr_sram: ddr-sram@1000 { 132 compatible = "rockchip,rk322x-ddr-sram"; 133 reg = <0x1000 0x8000>; 134 }; 135 }; 136 137 crypto: crypto@100a0000 { 138 compatible = "rockchip,rk322x-crypto"; 139 reg = <0x100a0000 0x10000>; 140 clock-names = "sclk_crypto"; 141 clocks = <&cru SCLK_CRYPTO>; 142 status = "disabled"; 143 }; 144 145 i2s1: i2s1@100b0000 { 146 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 147 reg = <0x100b0000 0x4000>; 148 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clock-names = "i2s_clk", "i2s_hclk"; 152 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 153 dmas = <&pdma 14>, <&pdma 15>; 154 dma-names = "tx", "rx"; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&i2s1_bus>; 157 status = "disabled"; 158 }; 159 160 i2s0: i2s0@100c0000 { 161 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 162 reg = <0x100c0000 0x4000>; 163 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clock-names = "i2s_clk", "i2s_hclk"; 167 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 168 dmas = <&pdma 11>, <&pdma 12>; 169 dma-names = "tx", "rx"; 170 status = "disabled"; 171 }; 172 173 i2s2: i2s2@100e0000 { 174 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 175 reg = <0x100e0000 0x4000>; 176 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 clock-names = "i2s_clk", "i2s_hclk"; 180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 181 dmas = <&pdma 0>, <&pdma 1>; 182 dma-names = "tx", "rx"; 183 status = "disabled"; 184 }; 185 186 grf: syscon@11000000 { 187 compatible = "rockchip,rk3228-grf", "syscon"; 188 reg = <0x11000000 0x1000>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 u2phy0: usb2-phy@760 { 193 compatible = "rockchip,rk322x-usb2phy"; 194 reg = <0x0760 0x0c>; 195 status = "disabled"; 196 197 u2phy0_otg: otg-port { 198 #phy-cells = <0>; 199 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "otg-bvalid", "otg-id", 203 "linestate"; 204 status = "disabled"; 205 }; 206 207 u2phy0_host: host-port { 208 #phy-cells = <0>; 209 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "linestate"; 211 status = "disabled"; 212 }; 213 }; 214 215 u2phy1: usb2-phy@800 { 216 compatible = "rockchip,rk322x-usb2phy"; 217 reg = <0x0800 0x0c>; 218 status = "disabled"; 219 220 u2phy1_otg: otg-port { 221 #phy-cells = <0>; 222 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 223 interrupt-names = "linestate"; 224 status = "disabled"; 225 }; 226 227 u2phy1_host: host-port { 228 #phy-cells = <0>; 229 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "linestate"; 231 status = "disabled"; 232 }; 233 }; 234 }; 235 236 uart0: serial@11010000 { 237 compatible = "snps,dw-apb-uart"; 238 reg = <0x11010000 0x100>; 239 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 240 clock-frequency = <24000000>; 241 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 242 clock-names = "baudclk", "apb_pclk"; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 245 reg-shift = <2>; 246 reg-io-width = <4>; 247 status = "disabled"; 248 }; 249 250 uart1: serial@11020000 { 251 compatible = "snps,dw-apb-uart"; 252 reg = <0x11020000 0x100>; 253 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 254 clock-frequency = <24000000>; 255 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 256 clock-names = "baudclk", "apb_pclk"; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&uart1_xfer>; 259 reg-shift = <2>; 260 reg-io-width = <4>; 261 status = "disabled"; 262 }; 263 264 uart2: serial@11030000 { 265 compatible = "snps,dw-apb-uart"; 266 reg = <0x11030000 0x100>; 267 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 268 clock-frequency = <24000000>; 269 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 270 clock-names = "baudclk", "apb_pclk"; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&uart21_xfer>; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 status = "disabled"; 276 }; 277 278 efuse: efuse@11040000 { 279 compatible = "rockchip,rk322x-efuse"; 280 reg = <0x11040000 0x20>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 clocks = <&cru PCLK_EFUSE_256>; 284 clock-names = "pclk_efuse"; 285 286 /* Data cells */ 287 efuse_id: id@7 { 288 reg = <0x7 0x10>; 289 }; 290 cpu_leakage: cpu_leakage@17 { 291 reg = <0x17 0x1>; 292 }; 293 }; 294 295 i2c0: i2c@11050000 { 296 compatible = "rockchip,rk3228-i2c"; 297 reg = <0x11050000 0x1000>; 298 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clock-names = "i2c"; 302 clocks = <&cru PCLK_I2C0>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c0_xfer>; 305 status = "disabled"; 306 }; 307 308 i2c1: i2c@11060000 { 309 compatible = "rockchip,rk3228-i2c"; 310 reg = <0x11060000 0x1000>; 311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clock-names = "i2c"; 315 clocks = <&cru PCLK_I2C1>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c1_xfer>; 318 status = "disabled"; 319 }; 320 321 i2c2: i2c@11070000 { 322 compatible = "rockchip,rk3228-i2c"; 323 reg = <0x11070000 0x1000>; 324 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clock-names = "i2c"; 328 clocks = <&cru PCLK_I2C2>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c2_xfer>; 331 status = "disabled"; 332 }; 333 334 i2c3: i2c@11080000 { 335 compatible = "rockchip,rk3228-i2c"; 336 reg = <0x11080000 0x1000>; 337 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clock-names = "i2c"; 341 clocks = <&cru PCLK_I2C3>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&i2c3_xfer>; 344 status = "disabled"; 345 }; 346 347 pwm0: pwm@110b0000 { 348 compatible = "rockchip,rk3288-pwm"; 349 reg = <0x110b0000 0x10>; 350 #pwm-cells = <3>; 351 clocks = <&cru PCLK_PWM>; 352 clock-names = "pwm"; 353 pinctrl-names = "active"; 354 pinctrl-0 = <&pwm0_pin>; 355 status = "disabled"; 356 }; 357 358 pwm1: pwm@110b0010 { 359 compatible = "rockchip,rk3288-pwm"; 360 reg = <0x110b0010 0x10>; 361 #pwm-cells = <3>; 362 clocks = <&cru PCLK_PWM>; 363 clock-names = "pwm"; 364 pinctrl-names = "active"; 365 pinctrl-0 = <&pwm1_pin>; 366 status = "disabled"; 367 }; 368 369 pwm2: pwm@110b0020 { 370 compatible = "rockchip,rk3288-pwm"; 371 reg = <0x110b0020 0x10>; 372 #pwm-cells = <3>; 373 clocks = <&cru PCLK_PWM>; 374 clock-names = "pwm"; 375 pinctrl-names = "active"; 376 pinctrl-0 = <&pwm2_pin>; 377 status = "disabled"; 378 }; 379 380 pwm3: pwm@110b0030 { 381 compatible = "rockchip,rk3288-pwm"; 382 reg = <0x110b0030 0x10>; 383 #pwm-cells = <2>; 384 clocks = <&cru PCLK_PWM>; 385 clock-names = "pwm"; 386 pinctrl-names = "active"; 387 pinctrl-0 = <&pwm3_pin>; 388 status = "disabled"; 389 }; 390 391 timer: timer@110c0000 { 392 compatible = "rockchip,rk3288-timer"; 393 reg = <0x110c0000 0x20>; 394 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&xin24m>, <&cru PCLK_TIMER>; 396 clock-names = "timer", "pclk"; 397 }; 398 399 cru: clock-controller@110e0000 { 400 compatible = "rockchip,rk3228-cru"; 401 reg = <0x110e0000 0x1000>; 402 rockchip,grf = <&grf>; 403 #clock-cells = <1>; 404 #reset-cells = <1>; 405 assigned-clocks = <&cru PLL_GPLL>; 406 assigned-clock-rates = <594000000>; 407 }; 408 409 thermal-zones { 410 cpu_thermal: cpu-thermal { 411 polling-delay-passive = <100>; /* milliseconds */ 412 polling-delay = <5000>; /* milliseconds */ 413 414 thermal-sensors = <&tsadc 0>; 415 416 trips { 417 cpu_alert0: cpu_alert0 { 418 temperature = <70000>; /* millicelsius */ 419 hysteresis = <2000>; /* millicelsius */ 420 type = "passive"; 421 }; 422 cpu_alert1: cpu_alert1 { 423 temperature = <75000>; /* millicelsius */ 424 hysteresis = <2000>; /* millicelsius */ 425 type = "passive"; 426 }; 427 cpu_crit: cpu_crit { 428 temperature = <90000>; /* millicelsius */ 429 hysteresis = <2000>; /* millicelsius */ 430 type = "critical"; 431 }; 432 }; 433 434 cooling-maps { 435 map0 { 436 trip = <&cpu_alert0>; 437 cooling-device = 438 <&cpu0 THERMAL_NO_LIMIT 6>; 439 }; 440 map1 { 441 trip = <&cpu_alert1>; 442 cooling-device = 443 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 444 }; 445 }; 446 }; 447 }; 448 449 tsadc: tsadc@11150000 { 450 compatible = "rockchip,rk3228-tsadc"; 451 reg = <0x11150000 0x100>; 452 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 454 clock-names = "tsadc", "apb_pclk"; 455 resets = <&cru SRST_TSADC>; 456 reset-names = "tsadc-apb"; 457 pinctrl-names = "init", "default", "sleep"; 458 pinctrl-0 = <&otp_gpio>; 459 pinctrl-1 = <&otp_out>; 460 pinctrl-2 = <&otp_gpio>; 461 #thermal-sensor-cells = <0>; 462 rockchip,hw-tshut-temp = <95000>; 463 status = "disabled"; 464 }; 465 466 sdmmc: dwmmc@30000000 { 467 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 468 reg = <0x30000000 0x4000>; 469 max-frequency = <150000000>; 470 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 472 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 473 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 474 fifo-depth = <0x100>; 475 cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 478 status = "disabled"; 479 }; 480 481 sdio: dwmmc@30010000 { 482 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 483 reg = <0x30010000 0x4000>; 484 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 486 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 487 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 488 fifo-depth = <0x100>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 491 status = "disabled"; 492 }; 493 494 emmc: dwmmc@30020000 { 495 compatible = "rockchip,rk3288-dw-mshc"; 496 reg = <0x30020000 0x4000>; 497 max-frequency = <150000000>; 498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 500 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 501 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 502 bus-width = <8>; 503 default-sample-phase = <158>; 504 num-slots = <1>; 505 fifo-depth = <0x100>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 508 resets = <&cru SRST_EMMC>; 509 reset-names = "reset"; 510 status = "disabled"; 511 }; 512 513 usb20_otg: usb@30040000 { 514 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 515 "snps,dwc2"; 516 reg = <0x30040000 0x40000>; 517 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 518 hnp-srp-disable; 519 dr_mode = "otg"; 520 phys = <&u2phy0_otg>; 521 phy-names = "usb2-phy"; 522 status = "disabled"; 523 }; 524 525 gmac: ethernet@30200000 { 526 compatible = "rockchip,rk3228-gmac"; 527 reg = <0x30200000 0x10000>; 528 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "macirq"; 530 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 531 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 532 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 533 <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; 534 clock-names = "stmmaceth", "mac_clk_rx", 535 "mac_clk_tx", "clk_mac_ref", 536 "clk_mac_refout", "aclk_mac", 537 "pclk_mac", "clk_macphy"; 538 resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; 539 reset-names = "stmmaceth", "mac-phy"; 540 rockchip,grf = <&grf>; 541 status = "disabled"; 542 }; 543 544 gic: interrupt-controller@32010000 { 545 compatible = "arm,gic-400"; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 #address-cells = <0>; 549 550 reg = <0x32011000 0x1000>, 551 <0x32012000 0x2000>, 552 <0x32014000 0x2000>, 553 <0x32016000 0x2000>; 554 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 555 }; 556 557 pinctrl: pinctrl { 558 compatible = "rockchip,rk3228-pinctrl"; 559 rockchip,grf = <&grf>; 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges; 563 564 gpio0: gpio0@11110000 { 565 compatible = "rockchip,gpio-bank"; 566 reg = <0x11110000 0x100>; 567 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cru PCLK_GPIO0>; 569 570 gpio-controller; 571 #gpio-cells = <2>; 572 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 }; 576 577 gpio1: gpio1@11120000 { 578 compatible = "rockchip,gpio-bank"; 579 reg = <0x11120000 0x100>; 580 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cru PCLK_GPIO1>; 582 583 gpio-controller; 584 #gpio-cells = <2>; 585 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 }; 589 590 gpio2: gpio2@11130000 { 591 compatible = "rockchip,gpio-bank"; 592 reg = <0x11130000 0x100>; 593 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru PCLK_GPIO2>; 595 596 gpio-controller; 597 #gpio-cells = <2>; 598 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 }; 602 603 gpio3: gpio3@11140000 { 604 compatible = "rockchip,gpio-bank"; 605 reg = <0x11140000 0x100>; 606 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&cru PCLK_GPIO3>; 608 609 gpio-controller; 610 #gpio-cells = <2>; 611 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 pcfg_pull_up: pcfg-pull-up { 617 bias-pull-up; 618 }; 619 620 pcfg_pull_down: pcfg-pull-down { 621 bias-pull-down; 622 }; 623 624 pcfg_pull_none: pcfg-pull-none { 625 bias-disable; 626 }; 627 628 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 629 drive-strength = <12>; 630 }; 631 632 sdmmc { 633 sdmmc_clk: sdmmc-clk { 634 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 635 }; 636 637 sdmmc_cmd: sdmmc-cmd { 638 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 639 }; 640 641 sdmmc_bus4: sdmmc-bus4 { 642 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 643 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 644 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 645 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 646 }; 647 }; 648 649 sdio { 650 sdio_clk: sdio-clk { 651 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 652 }; 653 654 sdio_cmd: sdio-cmd { 655 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 656 }; 657 658 sdio_bus4: sdio-bus4 { 659 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 660 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 661 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 662 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 663 }; 664 }; 665 666 emmc { 667 emmc_clk: emmc-clk { 668 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 669 }; 670 671 emmc_cmd: emmc-cmd { 672 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 673 }; 674 675 emmc_bus8: emmc-bus8 { 676 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 677 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 678 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 679 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 680 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 681 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 682 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 683 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 684 }; 685 }; 686 687 gmac { 688 rgmii_pins: rgmii-pins { 689 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 690 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 691 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 692 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 693 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 694 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 695 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 696 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 697 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 698 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 699 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 700 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 701 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 702 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 703 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 704 }; 705 706 rmii_pins: rmii-pins { 707 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 708 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 709 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 710 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 711 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 712 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 713 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 714 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 715 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 716 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 717 }; 718 719 phy_pins: phy-pins { 720 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 721 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 722 }; 723 }; 724 725 i2c0 { 726 i2c0_xfer: i2c0-xfer { 727 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 728 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 729 }; 730 }; 731 732 i2c1 { 733 i2c1_xfer: i2c1-xfer { 734 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 735 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 736 }; 737 }; 738 739 i2c2 { 740 i2c2_xfer: i2c2-xfer { 741 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 742 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 743 }; 744 }; 745 746 i2c3 { 747 i2c3_xfer: i2c3-xfer { 748 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 749 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 750 }; 751 }; 752 753 i2s1 { 754 i2s1_bus: i2s1-bus { 755 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 756 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 757 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 758 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 759 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 760 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 761 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 762 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 763 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 764 }; 765 }; 766 767 pwm0 { 768 pwm0_pin: pwm0-pin { 769 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 770 }; 771 }; 772 773 pwm1 { 774 pwm1_pin: pwm1-pin { 775 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 776 }; 777 }; 778 779 pwm2 { 780 pwm2_pin: pwm2-pin { 781 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 782 }; 783 }; 784 785 pwm3 { 786 pwm3_pin: pwm3-pin { 787 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 788 }; 789 }; 790 791 tsadc { 792 otp_gpio: otp-gpio { 793 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 794 }; 795 796 otp_out: otp-out { 797 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 798 }; 799 }; 800 801 uart0 { 802 uart0_xfer: uart0-xfer { 803 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 804 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 805 }; 806 807 uart0_cts: uart0-cts { 808 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 809 }; 810 811 uart0_rts: uart0-rts { 812 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 813 }; 814 }; 815 816 uart1 { 817 uart1_xfer: uart1-xfer { 818 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 819 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 820 }; 821 822 uart1_cts: uart1-cts { 823 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 824 }; 825 826 uart1_rts: uart1-rts { 827 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 828 }; 829 }; 830 831 uart2 { 832 uart2_xfer: uart2-xfer { 833 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, 834 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 835 }; 836 837 uart2_cts: uart2-cts { 838 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 839 }; 840 841 uart2_rts: uart2-rts { 842 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 843 }; 844 }; 845 846 uart2-1 { 847 uart21_xfer: uart21-xfer { 848 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, 849 <1 9 RK_FUNC_2 &pcfg_pull_none>; 850 }; 851 }; 852 }; 853 854 dmc: dmc@11200000 { 855 compatible = "rockchip,rk3228-dmc", "syscon"; 856 rockchip,cru = <&cru>; 857 rockchip,grf = <&grf>; 858 rockchip,msch = <&service_msch>; 859 reg = <0x11200000 0x3fc 860 0x12000000 0x400>; 861 rockchip,sram = <&ddr_sram>; 862 }; 863 864 service_msch: syscon@31090000 { 865 compatible = "rockchip,rk3228-msch", "syscon"; 866 reg = <0x31090000 0x2000>; 867 }; 868 869 nandc: nandc@30030000 { 870 compatible = "rockchip,rk-nandc"; 871 reg = <0x30030000 0x4000>; 872 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 873 nandc_id = <0>; 874 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 875 clock-names = "clk_nandc", "hclk_nandc"; 876 status = "disabled"; 877 }; 878}; 879