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/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c1729 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1741 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1743 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1748 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1750 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1640 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1660 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1663 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1670 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1673 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT2.c1681 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1693 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1700 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1702 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1541 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1561 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1564 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1571 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1574 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c1729 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1741 *BitErrPeriod_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1743 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1748 *BitErr_reg = reg; in INTERN_DVBT2_GetPostLdpcBer()
1749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1750 *BitErr_reg = (*BitErr_reg << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1640 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1660 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1663 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1670 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1673 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c1440 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1458 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1459 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1462 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1469 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1472 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c1394 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1413 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1415 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1416 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1422 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1423 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1425 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1426 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1428 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
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H A DhalDMD_INTERN_DVBT2.c1619 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1638 BitErrPeriod = reg; in INTERN_DVBT2_GetPostLdpcBer()
1639 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1640 BitErrPeriod = (BitErrPeriod << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1645 BitErr = reg; in INTERN_DVBT2_GetPostLdpcBer()
1646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1647 BitErr = (BitErr << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c1446 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1464 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1465 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1468 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1475 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1478 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1480 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c1783 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1802 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1805 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1812 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1815 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c1780 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1799 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1802 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1809 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1812 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
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H A DhalDMD_INTERN_DVBT2.c1678 MS_U8 reg=0; in INTERN_DVBT2_GetPostLdpcBer() local
1696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1697 BitErrPeriod = reg; in INTERN_DVBT2_GetPostLdpcBer()
1698 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 BitErrPeriod = (BitErrPeriod << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1704 BitErr = reg; in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1706 BitErr = (BitErr << 8) | reg; in INTERN_DVBT2_GetPostLdpcBer()
1707 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c1750 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1768 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1769 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1771 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1772 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1778 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1779 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1781 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1782 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1784 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c1777 MS_U8 reg=0, reg_frz=0; in INTERN_DVBT_GetPostViterbiBer() local
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1796 BitErrPeriod = reg; in INTERN_DVBT_GetPostViterbiBer()
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1799 BitErrPeriod = (BitErrPeriod << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1805 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1806 BitErr = reg; in INTERN_DVBT_GetPostViterbiBer()
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1809 BitErr = (BitErr << 8)|reg; in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
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