Searched refs:TSO_CLKGEN0_REG (Results 1 – 11 of 11) sorted by relevance
164 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL… macro540 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_TRACE_MASK; in HAL_TSO_PowerCtrl()541 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()542 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_PowerCtrl()548 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()549 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_TRACE_DISABLE; in HAL_TSO_PowerCtrl()550 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE; in HAL_TSO_PowerCtrl()721 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()769 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()821 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH… in HAL_TSO_GetInputTSIF_Status()[all …]
164 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL… macro549 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_TRACE_MASK; in HAL_TSO_PowerCtrl()550 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()551 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_PowerCtrl()557 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()558 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_TRACE_DISABLE; in HAL_TSO_PowerCtrl()559 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE; in HAL_TSO_PowerCtrl()742 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()790 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()842 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH… in HAL_TSO_GetInputTSIF_Status()[all …]
156 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL… macro481 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_TRACE_MASK; in HAL_TSO_PowerCtrl()482 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()483 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_PowerCtrl()489 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()490 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_TRACE_DISABLE; in HAL_TSO_PowerCtrl()491 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE; in HAL_TSO_PowerCtrl()686 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()727 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()773 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH… in HAL_TSO_GetInputTSIF_Status()[all …]
148 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL… macro658 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()699 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()745 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH… in HAL_TSO_GetInputTSIF_Status()749 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO1_IN_MASK) >> REG_CLKGEN2_TSO1_IN… in HAL_TSO_GetInputTSIF_Status()753 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO2_IN_MASK) >> REG_CLKGEN2_TSO2_IN… in HAL_TSO_GetInputTSIF_Status()870 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()874 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()877 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()878 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()[all …]
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2)))) macro424 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_GetInputTSIF_Status()495 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_Set_InClk()520 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()678 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()679 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()681 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) = in HAL_TSO_TSOOutDiv()682 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()686 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()687 …*pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK… in HAL_TSO_TSOOutDiv()[all …]
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2)))) macro422 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_GetInputTSIF_Status()496 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_Set_InClk()521 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()679 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()680 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()682 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) = in HAL_TSO_TSOOutDiv()683 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()687 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()688 …*pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK… in HAL_TSO_TSOOutDiv()[all …]
102 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2)))) macro425 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_GetInputTSIF_Status()499 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_Set_InClk()524 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()682 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()683 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()685 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) = in HAL_TSO_TSOOutDiv()686 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()690 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()691 …*pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK… in HAL_TSO_TSOOutDiv()[all …]
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2)))) macro424 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_GetInputTSIF_Status()498 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_Set_InClk()523 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()681 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()682 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()684 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) = in HAL_TSO_TSOOutDiv()685 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()689 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()690 …*pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK… in HAL_TSO_TSOOutDiv()[all …]