Lines Matching refs:TSO_CLKGEN0_REG
164 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL… macro
549 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_TRACE_MASK; in HAL_TSO_PowerCtrl()
550 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()
551 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_PowerCtrl()
557 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()
558 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_TRACE_DISABLE; in HAL_TSO_PowerCtrl()
559 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE; in HAL_TSO_PowerCtrl()
742 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()
790 TSO_CLKGEN0_REG(u16Reg) = u16value; in HAL_TSO_Set_InClk()
842 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH… in HAL_TSO_GetInputTSIF_Status()
973 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
977 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
980 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
981 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
996 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_PreTsoOutClk()
997 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe… in HAL_TSO_PreTsoOutClk()
1001 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) … in HAL_TSO_PreTsoOutClk()
1012 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) = in HAL_TSO_TSOOutDiv()
1013 … (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M; in HAL_TSO_TSOOutDiv()
1015 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_TSOOutDiv()
1016 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
1018 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
1019 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
1023 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
1024 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
1032 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()
1042 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) = in HAL_TSO_OutClk()
1043 … (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M; in HAL_TSO_OutClk()
1050 TSO_CLKGEN0_REG(REG_CLKGEN0_RESERVED0) |= REG_CLKGEN0_RES0_CLKTSO_TOPAD_INV; in HAL_TSO_OutClk()
1052 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk; in HAL_TSO_OutClk()
2113 _u16TSOTopReg[0][0] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN); in HAL_TSO_SaveRegs()
2114 _u16TSOTopReg[0][1] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE); in HAL_TSO_SaveRegs()
2115 _u16TSOTopReg[0][2] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK); in HAL_TSO_SaveRegs()
2116 _u16TSOTopReg[0][3] = TSO_CLKGEN0_REG(REG_CLKGEN0_RESERVED0); in HAL_TSO_SaveRegs()
2139 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) = _u16TSOTopReg[0][0]; in HAL_TSO_RestoreRegs()
2140 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = _u16TSOTopReg[0][1]; in HAL_TSO_RestoreRegs()
2141 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = _u16TSOTopReg[0][2]; in HAL_TSO_RestoreRegs()
2142 TSO_CLKGEN0_REG(REG_CLKGEN0_RESERVED0) = _u16TSOTopReg[0][3]; in HAL_TSO_RestoreRegs()