148 #define TSO_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL…  macro
658             u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask;  in HAL_TSO_Set_InClk()
699             TSO_CLKGEN0_REG(u16Reg) = u16value;  in HAL_TSO_Set_InClk()
745 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SH…  in HAL_TSO_GetInputTSIF_Status()
749 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO1_IN_MASK) >> REG_CLKGEN2_TSO1_IN…  in HAL_TSO_GetInputTSIF_Status()
753 …u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO2_IN_MASK) >> REG_CLKGEN2_TSO2_IN…  in HAL_TSO_GetInputTSIF_Status()
870         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;  in HAL_TSO_Set_TSOOut_Phase_Tune()
874 …     u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)  in HAL_TSO_Set_TSOOut_Phase_Tune()
877         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;  in HAL_TSO_Set_TSOOut_Phase_Tune()
878         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;  in HAL_TSO_Set_TSOOut_Phase_Tune()
893         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) =  in HAL_TSO_PreTsoOutClk()
894 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe…  in HAL_TSO_PreTsoOutClk()
898 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) …  in HAL_TSO_PreTsoOutClk()
909         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =  in HAL_TSO_TSOOutDiv()
910 …  (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;  in HAL_TSO_TSOOutDiv()
912         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) =  in HAL_TSO_TSOOutDiv()
913 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr…  in HAL_TSO_TSOOutDiv()
915         TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =  in HAL_TSO_TSOOutDiv()
916 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN…  in HAL_TSO_TSOOutDiv()
920 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;  in HAL_TSO_TSOOutDiv()
921 …  *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK;  in HAL_TSO_TSOOutDiv()
929     MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;  in HAL_TSO_OutClk()
939             TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =  in HAL_TSO_OutClk()
940 …  (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;  in HAL_TSO_OutClk()
947             TSO_CLKGEN0_REG(REG_CLKGEN0_RESERVED0) |= REG_CLKGEN0_RES0_CLKTSO_TOPAD_INV;  in HAL_TSO_OutClk()
949     TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;  in HAL_TSO_OutClk()