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Searched refs:TSO_CFG1_PKT_PARAM_LD (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tso/
H A DhalTSO.c1089 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1090 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1108 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1109 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1128 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1129 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1823 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
1824 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h313 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c1146 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1147 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1367 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1368 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1386 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1387 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1540 …(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1541 …(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
H A DregTSO.h445 #define TSO_CFG1_PKT_PARAM_LD 0x8000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c1146 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1147 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1367 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1368 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1386 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1387 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1540 …(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1541 …(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
H A DregTSO.h445 #define TSO_CFG1_PKT_PARAM_LD 0x8000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DhalTSO.c1225 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1226 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1244 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1245 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1264 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1265 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1924 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
1925 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h322 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c1178 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1179 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1401 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1402 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1420 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1421 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1574 …(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1575 …(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
H A DregTSO.h445 #define TSO_CFG1_PKT_PARAM_LD 0x8000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DhalTSO.c1278 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1279 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1297 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1298 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1317 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1318 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
2225 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
2226 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h320 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DhalTSO.c1303 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1304 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1322 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1323 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1342 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1343 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
2250 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
2251 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h323 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c1184 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1185 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1407 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1408 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1426 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1427 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1580 …(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1581 …(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DhalTSO.c1303 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1304 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1322 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1323 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1342 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1343 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
2250 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
2251 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h323 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DhalTSO.c1278 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1279 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1297 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1298 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1317 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1318 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
2225 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
2226 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD; in HAL_TSO_RestoreRegs()
H A DregTSO.h320 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c1187 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1188 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1410 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1411 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1429 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1430 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1583 …(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1584 …(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tso/
H A DhalTSO.c1034 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1035 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1053 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1054 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1073 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1074 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
H A DregTSO.h297 #define TSO_CFG1_PKT_PARAM_LD 0x8000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DhalTSO.c1197 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1198 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_ValidBlock_Count()
1216 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1217 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_InvalidBlock_Count()
1236 …EG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
1237 …16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_RW_OutputPktSize()
H A DregTSO.h322 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/drv/tso2/
H A DdrvTSO.c1664 HAL_TSO_Cfg1_Enable(0, TSO_CFG1_PKT_PARAM_LD, TRUE); in MDrv_TSO_Filein_Start()
1665 HAL_TSO_Cfg1_Enable(0, TSO_CFG1_PKT_PARAM_LD, FALSE); in MDrv_TSO_Filein_Start()

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