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Searched refs:TOP_CKG_VP8_288MHZ (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c3908 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3916 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3924 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3940 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3965 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h502 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c3906 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3911 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3916 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3941 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h519 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c3913 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3929 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3970 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h502 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c4007 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4015 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4023 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4031 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4064 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h533 #define TOP_CKG_VP8_288MHZ BITS(11:10, 2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3970 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3978 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4011 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h503 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c4004 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4012 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4020 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4028 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4061 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h504 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3959 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3964 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3969 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3989 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h503 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c3927 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h519 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3947 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3967 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h503 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h630 #define TOP_CKG_VP8_288MHZ BITS(3:2, 0) // default use this macro
H A DhalHVD_EX.c4251 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4267 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()