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Searched refs:REG_RVD_09_L (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c2751 W2BYTE(REG_RVD_09_L, 0x0800); //[13:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2795 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
2799 W2BYTE(REG_RVD_09_L, 0x0800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2803 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3859 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_SetOSDCOutputType()
H A DhalPNL.h211 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c2180 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2190 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
2195 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3158 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_SetOSDCOutputType()
H A DhalPNL.h209 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2748 W2BYTE(REG_RVD_09_L, 0x0800); //[13:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2792 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
2796 W2BYTE(REG_RVD_09_L, 0x0800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2800 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3905 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_SetOSDCOutputType()
H A DhalPNL.h218 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2748 W2BYTE(REG_RVD_09_L, 0x0800); //[13:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2792 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
2796 W2BYTE(REG_RVD_09_L, 0x0800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2800 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3905 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_SetOSDCOutputType()
H A DhalPNL.h218 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c2461 W2BYTE(REG_RVD_09_L, 0x0100); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
2517 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
2522 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3556 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_SetOSDCOutputType()
H A DhalPNL.h206 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h220 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
H A DhalPNL.c3635 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3645 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
3650 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h220 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
H A DhalPNL.c3662 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
3672 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
3677 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.h206 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
H A DhalPNL.c1798 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
1804 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.h206 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) macro
H A DhalPNL.c1798 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo in MHal_PNL_Init_XC_Clk()
1804 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+ in MHal_PNL_Init_XC_Clk()