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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT FALSE 117 118 // XC register serpead define 119 #define XC_REGISTER_SPREAD 1 120 #define SUPPORT_FRC 0 121 #define REG_CHIP_REVISION 0x1ECEUL //0x1ECFUL is high byte 122 #define XC_SUPPORT_AUTO_VSYNC 1 123 #define PNL_SUPPORT_DEVICE_NUM 2 124 #define MONACO_SC2 125 #define PNL_SUPPORT_2P_MODE TRUE 126 //------------------------------------------------------------------------------------------------- 127 // Driver Capability 128 //------------------------------------------------------------------------------------------------- 129 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 130 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 131 132 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 133 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 134 135 typedef struct 136 { 137 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 138 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 139 } PNL_HalInfo; 140 141 #define SUPPORT_OVERDRIVE 1 142 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 143 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING) 144 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 145 #define ENABLE_Auto_ModCurrentCalibration 1 146 147 // MIU Word (Bytes) 148 #define BYTE_PER_WORD (32) 149 150 #define SUPPORT_TCON TRUE 151 //------------------------------------------------------------------------------------------------- 152 // Macro and Define 153 //------------------------------------------------------------------------------------------------- 154 155 156 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 157 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 158 159 // NONPM 160 #define REG_RVD_BASE 0x100A00UL 161 #define REG_CHIPTOP_BASE 0x100B00UL // 0x1E00 - 0x1EFF 162 #if XC_REGISTER_SPREAD 163 #define REG_SCALER_BASE 0x130000UL 164 #else 165 #define REG_SCALER_BASE 0x102F00UL 166 #endif 167 #define REG_HDGEN_BASE 0x103000UL 168 #define REG_LPLL_BASE 0x103100UL 169 #define REG_MOD_BASE 0x103200UL 170 #define REG_MOD_A_BASE 0x111E00UL 171 #define REG_CLKGEN1_BASE 0x103300UL 172 #define REG_UTMI1_BASE 0x103A00UL 173 174 #define REG_CLKGEN0_BASE 0x100B00UL 175 #define REG_CLKGEN1_BASE 0x103300UL 176 177 178 /* TCON */ 179 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 180 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 181 182 /* LPLL */ 183 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 184 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 185 186 /* UTMI1 */ 187 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 188 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 189 190 191 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 192 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 193 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 194 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 195 196 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 197 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 198 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 199 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 200 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 201 #define REG_CLKGEN0_63_L (REG_CHIPTOP_BASE + 0xC6) 202 #define REG_CLKGEN0_7A_L (REG_CHIPTOP_BASE + 0xF4) 203 204 205 #define REG_CLKGEN1_31_L (REG_CLKGEN1_BASE + 0x62) 206 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) 207 208 209 210 #define XC_PAFRC_DITH_NOISEDITH_EN (0x00) 211 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 212 213 #define LVDS_DUAL_OUTPUT 0 214 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 215 #define LVDS_SINGLE_OUTPUT_A 2 216 #define LVDS_SINGLE_OUTPUT_B 3 217 #define LVDS_OUTPUT_User 4 218 219 // SCALER CLK select 220 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 221 #define CKG_ODCLK_GATED BIT(0) 222 #define CKG_ODCLK_INVERT BIT(1) 223 #define CKG_ODCLK_MASK (BIT(3) | BIT(2)) 224 #define CKG_ODCLK_CLK_SC_PLL (0 << 2) 225 #define CKG_ODCLK_CLK_LPLL_DIV_2 (1 << 2) 226 #define CKG_ODCLK_27M (2 << 2) 227 #define CKG_ODCLK_CLK_LPLL (3 << 2) 228 229 230 #define REG_CKG_BT656 REG_CLKGEN0_53_L 231 #define CKG_BT656_GATED BIT(8) 232 #define CKG_BT656_INVERT BIT(9) 233 #define CKG_BT656_MASK (BIT(11) | BIT(10)) 234 #define CKG_BT656_CLK_SC_PLL (0 << 10) 235 #define CKG_BT656_CLK_LPLL_DIV_2 (1 << 10) 236 #define CKG_BT656_27M (2 << 10) 237 #define CKG_BT656_CLK_LPLL (3 << 10) 238 239 #define REG_CKG_TX_MOD REG_CLKGEN0_58_L 240 #define CKG_TX_MOD_GATED BIT(0) 241 #define CKG_TX_MOD_INVERT BIT(1) 242 #define CKG_TX_MOD_MASK (BIT(3) | BIT(2)) 243 #define CKG_TX_1X_4XDIGITAL (0 << 2) 244 245 //clk setting be added in macan 246 //replace process start toggle in 4 bytes mode 247 #define REG_CKG_VBY1_VMODE REG_CLKGEN0_7A_L 248 #define CKG_VBY1_VMODE_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 249 #define CKG_VBY1_VMODE_LPLL_CLK (0 << 3) // clk from scaler 250 #define CKG_VBY1_VMODE_LPLL_FIFO (0x08) 251 #define CKG_VBY1_VMODE_LPLL_FIFO_DIV2 (0x09) 252 #define CKG_VBY1_VMODE_LPLL_FIFO_DIV4 (0x0A) 253 #define CKG_VBY1_VMODE_LPLL_FIFO_DIV8 (0x0B) 254 255 //clk setting be added in macan 256 //separate mod analog clk 257 #define REG_CKG_ODCLK_A REG_CLKGEN0_7A_L 258 #define CKG_ODCLK_A_GATED (BIT(4)) 259 #define CKG_ODCLK_A_INVERT (BIT(5)) 260 #define CKG_ODCLK_A_MASK (BIT(7) | BIT(6)) 261 #define CKG_ODCLK_A_CLK_DIV2 (1 << 6) 262 #define CKG_ODCLK_A_CLK (3 << 6) 263 264 //clk setting be added in macan 265 //used in tcon 266 #define REG_CKG_NOSSC_ODCLK REG_CLKGEN0_7A_L 267 #define CKG_NOSSC_ODCLK_GATED (BIT(8)) 268 #define CKG_NOSSC_ODCLK_INVERT (BIT(9)) 269 #define CKG_NOSSC_ODCLK_MASK (BIT(11) | BIT(10)) 270 #define CKG_NOSSC_ODCLK_CLK_DIV2 (1 << 10) 271 #define CKG_NOSSC_ODCLK_CLK (3 << 10) 272 273 274 275 #define PANEL_LPLL_INPUT_DIV_1st 0x00 276 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 277 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 278 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 279 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 280 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 281 282 #define LVDS_MPLL_CLOCK_MHZ 432 // For crystal 24Mhz 283 #define LVDS_SPAN_FACTOR 131072 284 285 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 286 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 287 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 288 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 289 290 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 291 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 292 293 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 294 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 295 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 296 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 297 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 298 299 #define SUPPORT_MOD_ADBANK_SEPARATE 300 301 #define SUPPORT_VBY1_HWTRAINING_MODE 302 303 //for auto set output config and clk according to pin mapping 304 #define CONFIG_FOR_VBY1_DATA 0x01 305 #define CONFIG_FOR_VBY1_DATA_BIT_NUM 2 306 307 #define VBY1_CLK_TBL_ROW 4 308 309 #define USE_PANEL_GAMMA 310 311 //------------------------------------------------------------------------------------------------- 312 // Type and Structure 313 //------------------------------------------------------------------------------------------------- 314 typedef enum 315 { 316 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 317 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0x80 318 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 319 320 typedef enum 321 { 322 E_DRVPNL_ALLIN_MODE = 1, 323 E_DRVPNL_2X_MODE = 2, 324 E_DRVPNL_SEPARATE_MODE = 3, 325 E_DRVPNL_TYPE_NUM 326 }DRVPNL_OUT_SWING_TYPE; 327 328 typedef enum 329 { 330 HAL_TI_10BIT_MODE = 0, 331 HAL_TI_8BIT_MODE = 2, 332 HAL_TI_6BIT_MODE = 3, 333 } PNL_HAL_TIMODES; 334 335 //------------------------------------------------------------------------------------------------- 336 // Function and Variable 337 //------------------------------------------------------------------------------------------------- 338 HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr; 339 HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr; 340 341 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 342 void MHal_PNL_TCON_Init(void *pInstance); 343 344 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 345 346 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 347 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 348 void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13); 349 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 350 351 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 352 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 353 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 354 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 355 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 356 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); 357 #ifdef MONACO_SC2 358 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode ); 359 #endif 360 #define Hal_PNL_Get12BitGammaPerChannel(args...) 361 //void _MDrv_PNL_Set_12BIT_Gamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab); 362 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src); 363 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 364 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 365 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 366 367 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 368 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 369 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 370 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit, MS_U8 u8MIUSel); 371 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 372 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 373 374 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 375 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 376 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 377 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 378 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 379 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select); 380 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 381 382 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 383 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 384 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 385 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 386 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 387 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 388 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 389 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 390 391 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 392 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz); 393 394 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 395 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 396 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 397 398 399 /// Set pair swap for user mode 400 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 401 402 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 403 404 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz); 405 406 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance); 407 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance); 408 409 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 410 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 411 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat); 412 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 413 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 414 415 void MHal_PNL_Set_T3D_Setting(void *pInstance); 416 417 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 418 void MHal_PNL_Init(void *pInstance); 419 void MHal_PNL_Bringup(void *pInstance); 420 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance); 421 422 MS_U16 MHal_PNL_GetPanelVStart(void); 423 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance); 424 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable); 425 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance); 426 void MHal_PNL_TCON_Patch(void); 427 428 429 #ifdef __cplusplus 430 } 431 #endif 432 433 #endif // _HAL_PNL_H_ 434 435