1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT FALSE 117 118 // XC register serpead define 119 #define XC_REGISTER_SPREAD 1 120 #define SUPPORT_FRC 0 121 #define REG_CHIP_REVISION 0x1ECEUL //0x1ECFUL is high byte 122 #define XC_SUPPORT_AUTO_VSYNC 1 123 #define PNL_SUPPORT_DEVICE_NUM 2 124 #define MONACO_SC2 125 #define PNL_SUPPORT_2P_MODE TRUE 126 //------------------------------------------------------------------------------------------------- 127 // Driver Capability 128 //------------------------------------------------------------------------------------------------- 129 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 130 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 131 132 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 133 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 134 135 typedef struct 136 { 137 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 138 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 139 } PNL_HalInfo; 140 141 #define SUPPORT_OVERDRIVE 1 142 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 143 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING) 144 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 145 #define ENABLE_Auto_ModCurrentCalibration 1 146 147 // MIU Word (Bytes) 148 #define BYTE_PER_WORD (32) 149 150 #define SUPPORT_TCON TRUE 151 152 //#define MOD_TVFRC //for sub bank register change 153 //------------------------------------------------------------------------------------------------- 154 // Macro and Define 155 //------------------------------------------------------------------------------------------------- 156 157 158 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 159 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 160 161 // NONPM 162 #define REG_RVD_BASE 0x100A00UL 163 #define REG_CHIPTOP_BASE 0x100B00UL // 0x1E00 - 0x1EFF 164 #if XC_REGISTER_SPREAD 165 #define REG_SCALER_BASE 0x130000UL 166 #else 167 #define REG_SCALER_BASE 0x102F00UL 168 #endif 169 #define REG_HDGEN_BASE 0x103000UL 170 #define REG_LPLL_BASE 0x103100UL 171 #define REG_MOD_BASE 0x103200UL 172 #define REG_MOD_A_BASE 0x111E00UL 173 #define REG_CLKGEN1_BASE 0x103300UL 174 #define REG_UTMI1_BASE 0x103A00UL 175 176 #define REG_CLKGEN0_BASE 0x100B00UL 177 #define REG_CLKGEN1_BASE 0x103300UL 178 179 #define REG_CHIP_BASE 0x101E00UL 180 181 #define REG_SC2_BASE 0x103000UL 182 #define REG_XC_EXT_BASE 0x302F00UL 183 184 185 /* TCON */ 186 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 187 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 188 189 /* LPLL */ 190 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 191 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 192 193 /* UTMI1 */ 194 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 195 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 196 197 198 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 199 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 200 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 201 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 202 203 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 204 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 205 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 206 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 207 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 208 #define REG_CLKGEN0_63_L (REG_CHIPTOP_BASE + 0xC6) 209 210 #define REG_CLKGEN1_31_L (REG_CLKGEN1_BASE + 0x62) 211 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) 212 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) 213 #define REG_RVD_44_L (REG_RVD_BASE + 0x88) 214 215 #define REG_CHIP_50_L (REG_CHIP_BASE + 0xA0) 216 217 #define REG_SC2_00_L (REG_SC2_BASE + 0x00) 218 #define REG_SC2_03_L (REG_SC2_BASE + 0x06) 219 220 #define XC_PAFRC_DITH_NOISEDITH_EN (0x00) 221 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 222 223 #define LVDS_DUAL_OUTPUT 0 224 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 225 #define LVDS_SINGLE_OUTPUT_A 2 226 #define LVDS_SINGLE_OUTPUT_B 3 227 #define LVDS_OUTPUT_User 4 228 229 // SCALER CLK select 230 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 231 #define CKG_ODCLK_GATED BIT(0) 232 #define CKG_ODCLK_INVERT BIT(1) 233 #define CKG_ODCLK_SEL_SOURCE BIT(2) 234 #define CKG_ODCLK_SEL_SYNTHETIC (0 << 2) 235 #define CKG_ODCLK_SEL_LPLL (1 << 2) 236 #define CKG_ODCLK_MASK (BIT(3) | BIT(4)) 237 #define CKG_ODCLK_CLK_DIV_2 (0 << 3) 238 #define CKG_ODCLK_XTAL (1 << 3) 239 #define CKG_ODCLK_CLK_DIV_4 (2 << 3) 240 #define CKG_ODCLK_CLK_LPLL (3 << 3) 241 242 243 #define REG_CKG_ODCLK_MFT REG_CLKGEN0_53_L 244 #define CKG_ODCLK_MFT_GATED BIT(4) 245 #define CKG_ODCLK_MFT_INVERT BIT(5) 246 #define CKG_ODCLK_MFT_SEL_SOURCE BIT(6) 247 #define CKG_ODCLK_MFT_SEL_SYNTHETIC (0 << 6) 248 #define CKG_ODCLK_MFT_SEL_LPLL (1 << 6) 249 #define CKG_ODCLK_MFT_MASK (BIT(7) | BIT(8)) 250 #define CKG_ODCLK_MFT_CLK_DIV_2 (0 << 7) 251 #define CKG_ODCLK_MFT_XTAL (1 << 7) 252 #define CKG_ODCLK_MFT_CLK_DIV_4 (2 << 7) 253 #define CKG_ODCLK_MFT_CLK_LPLL (3 << 7) 254 255 #define REG_CKG_BT656 REG_CLKGEN0_53_L 256 #define CKG_BT656_GATED BIT(8) 257 #define CKG_BT656_INVERT BIT(9) 258 #define CKG_BT656_MASK (BIT(11) | BIT(10)) 259 #define CKG_BT656_CLK_SC_PLL (0 << 10) 260 #define CKG_BT656_CLK_LPLL_DIV_2 (1 << 10) 261 #define CKG_BT656_27M (2 << 10) 262 #define CKG_BT656_CLK_LPLL (3 << 10) 263 264 #define REG_CKG_TX_MOD REG_CLKGEN0_58_L 265 #define CKG_TX_MOD_GATED BIT(0) 266 #define CKG_TX_MOD_INVERT BIT(1) 267 #define CKG_TX_MOD_MASK (BIT(3) | BIT(2)) 268 #define CKG_TX_1X_4XDIGITAL (0 << 2) 269 270 #define PANEL_LPLL_INPUT_DIV_1st 0x00 271 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 272 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 273 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 274 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 275 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 276 277 #define LVDS_MPLL_CLOCK_MHZ 432 // For crystal 24Mhz 278 #define LVDS_SPAN_FACTOR 131072 279 280 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 281 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 282 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 283 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 284 285 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 286 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 287 288 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 289 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 290 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 291 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 292 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 293 294 #define SUPPORT_MOD_ADBANK_SEPARATE 295 296 #define SUPPORT_VBY1_HWTRAINING_MODE 297 298 299 //for auto set output config and clk according to pin mapping 300 #define CONFIG_FOR_VBY1_DATA 0x01 301 #define CONFIG_FOR_VBY1_DATA_BIT_NUM 2 302 303 #define VBY1_CLK_TBL_ROW 4 304 305 //------------------------------------------------------------------------------------------------- 306 // Type and Structure 307 //------------------------------------------------------------------------------------------------- 308 typedef enum 309 { 310 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 311 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0x80 312 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 313 314 typedef enum 315 { 316 E_DRVPNL_ALLIN_MODE = 1, 317 E_DRVPNL_2X_MODE = 2, 318 E_DRVPNL_SEPARATE_MODE = 3, 319 E_DRVPNL_TYPE_NUM 320 }DRVPNL_OUT_SWING_TYPE; 321 322 typedef enum 323 { 324 HAL_TI_10BIT_MODE = 0, 325 HAL_TI_8BIT_MODE = 2, 326 HAL_TI_6BIT_MODE = 3, 327 } PNL_HAL_TIMODES; 328 329 //------------------------------------------------------------------------------------------------- 330 // Function and Variable 331 //------------------------------------------------------------------------------------------------- 332 HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr; 333 HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr; 334 335 #ifdef REG_XC_EXT_BASE 336 HAL_PNL_INTERFACE MS_VIRT g_ptr_XCExtendRiuBaseAddr; 337 #endif 338 339 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 340 void MHal_PNL_TCON_Init(void *pInstance); 341 342 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 343 344 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 345 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 346 void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13); 347 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 348 349 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 350 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 351 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 352 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 353 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 354 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); 355 #ifdef MONACO_SC2 356 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode ); 357 #endif 358 #define Hal_PNL_Get12BitGammaPerChannel(args...) 359 //void _MDrv_PNL_Set_12BIT_Gamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab); 360 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src); 361 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 362 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 363 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 364 365 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 366 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 367 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 368 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit, MS_U8 u8MIUSel); 369 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 370 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 371 372 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 373 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 374 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 375 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 376 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 377 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select); 378 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 379 380 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 381 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 382 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 383 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 384 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 385 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 386 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 387 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 388 389 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 390 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz); 391 392 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 393 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 394 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 395 396 397 /// Set pair swap for user mode 398 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 399 400 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 401 402 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz); 403 404 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance); 405 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance); 406 407 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 408 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 409 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat); 410 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 411 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 412 413 void MHal_PNL_Set_T3D_Setting(void *pInstance); 414 415 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 416 void MHal_PNL_Init(void *pInstance); 417 void MHal_PNL_Bringup(void *pInstance); 418 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance); 419 420 MS_U16 MHal_PNL_GetPanelVStart(void); 421 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance); 422 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable); 423 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance); 424 void MHal_PNL_TCON_Patch(void* pInstance); 425 426 427 #ifdef __cplusplus 428 } 429 #endif 430 431 #endif // _HAL_PNL_H_ 432 433