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Searched refs:MIU2_REG_RQ0_MASK (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DhalVPU_EX.c266 …pu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU2…
267 …pu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU2…
268 …u,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(3));}):({_VPU_WriteRegBit(MIU2…
H A DregVPU_EX.h443 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h417 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalVPU_EX.c249 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
250 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
251 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalVPU_EX.c257 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
258 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
259 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h445 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalVPU_EX.c262 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
263 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
264 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h445 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalVPU_EX.c263 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
264 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
265 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h632 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalHVD_EX.c232 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalHVD_EX.c232 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h634 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalHVD_EX.c218 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h632 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalHVD_EX.c233 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h676 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro
H A DhalHVD_EX.c228 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h660 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) macro