1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114 #include "drvSYS.h"
115
116
117 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
118
119 // Internal Definition
120 #include "regVPU_EX.h"
121 #include "halVPU_EX.h"
122 #include "halCHIP.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147
148
149 #ifdef MSOS_TYPE_LINUX_KERNEL
150 #define VPRINTF printk
151 #else
152 #ifndef ANDROID
153 #define VPRINTF printf
154 #else
155 #include <sys/mman.h>
156 #include <cutils/ashmem.h>
157 #include <cutils/log.h>
158 #define VPRINTF ALOGD
159 #endif
160 #endif
161
162
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216
217 #define VPU_MSG_ERR(format, args...) \
218 do \
219 { \
220 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
221 { \
222 printf("[VPU][ERR]%s:", __FUNCTION__); \
223 printf(format, ##args); \
224 } \
225 } while (0)
226
227 #define VPU_MSG_DBG(format, args...) \
228 do \
229 { \
230 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
231 { \
232 printf("[VPU][DBG]%s:", __FUNCTION__); \
233 printf(format, ##args); \
234 } \
235 } while (0)
236
237 #define VPU_MSG_INFO(format, args...) \
238 do \
239 { \
240 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
241 { \
242 printf("[VPU][INF]%s:", __FUNCTION__); \
243 printf(format, ##args); \
244 } \
245 } while (0)
246
247 //------------------------------ MIU SETTINGS ----------------------------------
248 #ifdef EVDR2
249 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
250 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
251 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))
252
253 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
254 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
255 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
256
257 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
258 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
259 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
260
261
262 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
263 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
264 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
265 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
266 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
267 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
268 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
269 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
270 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))) //g08
271 #endif
272
273
274
275 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
276 do \
277 { \
278 if (miu_clients##_ON_MIU0 == 1) \
279 { \
280 _MaskMiuReq_##miu_clients(mask); \
281 } \
282 else \
283 { \
284 if (miu_clients##_ON_MIU1 == 1) \
285 { \
286 _MaskMiu1Req_##miu_clients(mask); \
287 } \
288 else if (miu_clients##_ON_MIU2 == 1) \
289 { \
290 _MaskMiu2Req_##miu_clients(mask); \
291 } \
292 } \
293 } while(0)
294
295
296
297
298 #if ENABLE_VPU_MUTEX_PROTECTION
299 static MS_S32 s32VPUMutexID = -1;
300 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
301
302 #define _HAL_VPU_MutexCreate() \
303 if (s32VPUMutexID < 0) \
304 { \
305 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
306 }
307
308 #define _HAL_VPU_MutexDelete() \
309 if (s32VPUMutexID >= 0) \
310 { \
311 MsOS_DeleteMutex(s32VPUMutexID); \
312 s32VPUMutexID = -1; \
313 }
314
315 #define _HAL_VPU_Entry() \
316 if (s32VPUMutexID >= 0) \
317 { \
318 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
319 { \
320 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
321 } \
322 }
323
324 #define _HAL_VPU_Return(_ret) \
325 { \
326 if (s32VPUMutexID >= 0) \
327 { \
328 MsOS_ReleaseMutex(s32VPUMutexID); \
329 } \
330 return _ret; \
331 }
332
333 #define _HAL_VPU_Release() \
334 { \
335 if (s32VPUMutexID >= 0) \
336 { \
337 MsOS_ReleaseMutex(s32VPUMutexID); \
338 } \
339 }
340 #else
341 #define _HAL_VPU_MutexCreate()
342 #define _HAL_VPU_MutexDelete()
343 #define _HAL_VPU_Entry()
344 #define _HAL_VPU_Return(_ret) {return _ret;}
345 #define _HAL_VPU_Release()
346 #endif
347
348 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
349 #define VPU_CMD_TIMEOUT 1000 // 1 sec
350
351 //-------------------------------------------------------------------------------------------------
352 // Local Structures
353 //-------------------------------------------------------------------------------------------------
354 typedef struct _VPU_HWInitFunc
355 {
356 MS_BOOL (*pfMVDHW_Init)(void);
357 MS_BOOL (*pfMVDHW_Deinit)(void);
358 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
359 MS_BOOL (*pfHVDHW_Deinit)(void);
360 } VPU_HWInitFunc;
361
362 typedef struct
363 {
364 MS_U32 u32ApiHW_Version; //<Version of current structure>
365 MS_U16 u16ApiHW_Length; //<Length of this structure>
366
367 MS_U8 u8Cap_Support_Decoder_Num;
368
369 MS_BOOL bCap_Support_MPEG2;
370 MS_BOOL bCap_Support_H263;
371 MS_BOOL bCap_Support_MPEG4;
372 MS_BOOL bCap_Support_DIVX311;
373 MS_BOOL bCap_Support_DIVX412;
374 MS_BOOL bCap_Support_FLV;
375 MS_BOOL bCap_Support_VC1ADV;
376 MS_BOOL bCap_Support_VC1MAIN;
377
378 MS_BOOL bCap_Support_RV8;
379 MS_BOOL bCap_Support_RV9;
380 MS_BOOL bCap_Support_H264;
381 MS_BOOL bCap_Support_AVS;
382 MS_BOOL bCap_Support_AVS_PLUS;
383 MS_BOOL bCap_Support_MJPEG;
384 MS_BOOL bCap_Support_MVC;
385 MS_BOOL bCap_Support_VP8;
386 MS_BOOL bCap_Support_VP9;
387 MS_BOOL bCap_Support_HEVC;
388
389 /*New HW Cap and Feature add in struct at the end*/
390 }VDEC_HwCap;
391
392 //-------------------------------------------------------------------------------------------------
393 // Local Functions Prototype
394 //-------------------------------------------------------------------------------------------------
395 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
396 static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
397 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
398
399 //-------------------------------------------------------------------------------------------------
400 // Global Variables
401 //-------------------------------------------------------------------------------------------------
402 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
403 extern MS_BOOL HAL_MVD_InitHW(void);
404 extern MS_BOOL HAL_MVD_DeinitHW(void);
405 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
406 extern MS_BOOL HAL_HVD_EX_DeinitHW(void);
407 extern void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
408 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
409 #if SUPPORT_G2VP9 && defined(VDEC3)
410 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
411 #endif
412 #if defined (__aeon__)
413 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
414 #else
415 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
416 #endif
417
418 //-------------------------------------------------------------------------------------------------
419 // Local Variables
420 //-------------------------------------------------------------------------------------------------
421 #if 0
422
423 static MS_BOOL _bVPUPowered = FALSE;
424 static MS_BOOL _bVPURsted = FALSE;
425 static MS_BOOL _bVPUSingleMode = FALSE;
426 static VPU_EX_DecModCfg _stVPUDecMode;
427
428 static MS_U8 u8TaskCnt = 0;
429
430 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
431
432 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
433 static VPU_EX_Stream _stVPUStream[] =
434 {
435 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
436 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
437 };
438 static VPU_HWInitFunc stHWInitFunc =
439 {
440 &HAL_MVD_InitHW,
441 &HAL_MVD_DeinitHW,
442 &HAL_HVD_EX_InitHW,
443 &HAL_HVD_EX_DeinitHW,
444 };
445
446 #endif
447
448 #if VPU_ENABLE_EMBEDDED_FW_BINARY
449 static const MS_U8 u8HVD_FW_Binary[] = {
450 #include "fwVPU.dat"
451 };
452
453 #if HVD_ENABLE_RV_FEATURE
454 static const MS_U8 u8HVD_VLC_Binary[] = {
455 #include "fwVPU_VLC.dat"
456 };
457 #endif
458 #endif
459
460
461 #ifdef VDEC3
462 typedef struct
463 {
464 MS_BOOL bTSP;
465 MS_U32 u32Used;
466 } BBU_STATE;
467
468 typedef struct
469 {
470 MS_BOOL bTSP;
471 MS_BOOL bUsedbyMVD;
472 MS_U32 u32Used;
473 } SLQ_STATE;
474 #endif
475
476 typedef struct
477 {
478 MS_BOOL _bVPUPowered;
479 MS_BOOL _bVPURsted;
480 MS_BOOL _bVPUSingleMode;
481 VPU_EX_DecModCfg _stVPUDecMode;
482 MS_U8 u8TaskCnt;
483 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
484 #ifdef VDEC3
485 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
486 #else
487 VPU_EX_Stream _stVPUStream[2];
488 #endif
489
490 VPU_HWInitFunc stHWInitFunc;
491
492 MS_BOOL bVpuExReloadFW;
493 MS_BOOL bVpuExLoadFWRlt;
494 MS_VIRT u32VPUSHMAddr; //PA
495 MS_BOOL bEnableVPUSecureMode;
496
497 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
498 MS_BOOL bEnableDymanicFBMode;
499 MS_PHY u32DynamicFBAddress;
500 MS_U32 u32DynamicFBSize;
501 #ifdef VDEC3
502 MS_VIRT u32FWCodeAddr;
503 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
504
505 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
506 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
507 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
508
509 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
510 #endif
511 MS_U8 u8ForceRst;
512 } VPU_Hal_CTX;
513
514 //global variables
515 VPU_Hal_CTX* pVPUHalContext = NULL;
516 VPU_Hal_CTX gVPUHalContext;
517 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
518 MS_BOOL bVPUMbxInitFlag = 0;
519 MS_U8 u8VPUMbxMsgClass = 0;
520 MBX_Msg VPUReeToTeeMbxMsg;
521 MBX_Msg VPUTeeToReeMbxMsg;
522
523 //-------------------------------------------------------------------------------------------------
524 // Debug Functions
525 //-------------------------------------------------------------------------------------------------
526
527
528 //-------------------------------------------------------------------------------------------------
529 // Local Functions
530 //-------------------------------------------------------------------------------------------------
531
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)532 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
533 {
534 #if HVD_ENABLE_RV_FEATURE
535 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
536 {
537 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
538 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
539 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
540
541 if (pVlcCfg->u32BinSize)
542 {
543 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
544
545 MS_U32 u32Start;
546 MS_U32 u32StartOffset;
547 MS_U8 u8MiuSel;
548
549 // Get MIU selection and offset from physical address = 0x30000000
550 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
551
552
553 if(u8MiuSel == E_CHIP_MIU_0)
554 cpyflag = E_SPIDMA_DEV_MIU0;
555 else if(u8MiuSel == E_CHIP_MIU_1)
556 cpyflag = E_SPIDMA_DEV_MIU1;
557 else if(u8MiuSel == E_CHIP_MIU_2)
558 cpyflag = E_SPIDMA_DEV_MIU2;
559
560 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
561 {
562 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
563 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
564
565 return FALSE;
566 }
567 }
568 else
569 {
570 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
571 return FALSE;
572 }
573 #else
574 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
575 return FALSE;
576 #endif
577 }
578 else
579 {
580 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
581 {
582 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
583 {
584 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
585 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
586
587 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
588 BDMA_Result bdmaRlt;
589 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
590
591 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
592 u32SrcAdd = pVlcCfg->u32BinAddr;
593 u32tabsize = pVlcCfg->u32BinSize;
594 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
595 MsOS_FlushMemory();
596 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
597
598 if (E_BDMA_OK != bdmaRlt)
599 {
600 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
601 }
602 #else
603 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
604 #endif
605 }
606 else
607 {
608 VPU_MSG_ERR
609 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
610 return FALSE;
611 }
612 }
613 else
614 {
615 #if VPU_ENABLE_EMBEDDED_FW_BINARY
616 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
617 MS_U8 *pu8HVD_VLC_Binary;
618
619 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
620
621 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
622 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
623 (MS_U32) sizeof(u8HVD_VLC_Binary));
624
625 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
626 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
627 #else
628 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
629 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
630 (MS_U32) sizeof(u8HVD_VLC_Binary));
631
632 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
633 #endif
634 #else
635 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
636 return FALSE;
637 #endif
638 }
639 }
640 #endif
641
642 return TRUE;
643 }
644
645 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)646 static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
647 {
648 MS_U8 u8OffsetIdx = 0;
649 MS_U8 u8VSidBaseMask = 0xF0;
650 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
651
652 switch (eVSidBase)
653 {
654 case E_HAL_VPU_MAIN_STREAM_BASE:
655 {
656 u8OffsetIdx = 0;
657 break;
658 }
659 case E_HAL_VPU_SUB_STREAM_BASE:
660 {
661 u8OffsetIdx = 1;
662 break;
663 }
664 case E_HAL_VPU_MVC_STREAM_BASE:
665 {
666 u8OffsetIdx = 0;
667 break;
668 }
669 #ifdef VDEC3
670 case E_HAL_VPU_N_STREAM_BASE:
671 {
672 u8OffsetIdx = u32Id & 0x0F;
673 break;
674 }
675 #endif
676 default:
677 {
678 u8OffsetIdx = 0;
679 break;
680 }
681 }
682
683 /*
684 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
685 u32Id, eVSidBase, u8OffsetIdx);
686 */
687 return u8OffsetIdx;
688 }
689
_VPU_EX_Context_Init(void)690 static void _VPU_EX_Context_Init(void)
691 {
692 #ifdef VDEC3
693 MS_U8 i;
694
695 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
696 {
697 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
698 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
699 }
700
701 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
702 {
703 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
704 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
705 }
706
707 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
708 {
709 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
710 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
711 }
712
713 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
714 {
715 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
716 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
717 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
718 }
719 #else
720 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
721 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
722 #endif
723 pVPUHalContext->bVpuExReloadFW = TRUE;
724 pVPUHalContext->u8ForceRst = 0;
725
726 }
727
HAL_VPU_EX_ForceSwRst(void)728 void HAL_VPU_EX_ForceSwRst(void)
729 {
730 pVPUHalContext->u8ForceRst = 1;
731 }
732
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)733 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
734 {
735 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
736 MS_U8 u8OffsetIdx = 0;
737
738 if (NULL == pTaskInfo)
739 {
740 return eCmd;
741 }
742
743 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
744
745 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
746 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
747
748 #ifdef VDEC3
749 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
750 {
751 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
752 {
753 eCmd = E_NST_CMD_TASK_MVD_TSP;
754 }
755 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
756 {
757 eCmd = E_NST_CMD_TASK_MVD_SLQ;
758 }
759 }
760 #else
761 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
762 {
763 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
764 {
765 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
766 }
767 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
768 {
769 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
770 }
771 }
772 #endif
773 #ifdef VDEC3
774 #if SUPPORT_G2VP9
775 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
776 #else
777 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
778 #endif
779 {
780 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
781 {
782 eCmd = E_NST_CMD_TASK_HVD_TSP;
783 }
784 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
785 {
786 eCmd = E_NST_CMD_TASK_HVD_BBU;
787 }
788 }
789 #else
790 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
791 {
792 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
793 {
794 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
795 }
796 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
797 {
798 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
799 }
800 }
801 #endif
802
803 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
804 return eCmd;
805 }
806
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)807 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
808 {
809 if (!pTaskInfo)
810 {
811 VPU_MSG_ERR("null input\n");
812 return FALSE;
813 }
814
815 //Check if we need to init MVD HW
816 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
817 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
818 {
819 //Init HW
820 if (FALSE == HAL_VPU_EX_MVDInUsed())
821 {
822 if (TRUE != HAL_MVD_InitHW())
823 {
824 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
825 return FALSE;
826 }
827 }
828 else
829 {
830 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
831 }
832 }
833
834 //MVD use sub mvop
835 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
836 #ifdef VDEC3
837 (pTaskInfo->u8HalId == 1) )
838 #else
839 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
840 #endif
841 {
842 VPU_MSG_ERR("Force turn on HVD\n");
843 if(!HAL_VPU_EX_HVDInUsed())
844 {
845 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
846 {
847 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
848 {
849 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
850 return FALSE;
851 }
852 }
853 else
854 {
855 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
856 HAL_HVD_EX_PowerCtrl(TRUE);
857 }
858 }
859 else
860 {
861 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
862 }
863 }
864
865 //Check if we need to init HVD HW
866 #ifdef VDEC3
867 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
868 #else
869 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
870 #endif
871 {
872 if (!HAL_VPU_EX_MVDInUsed())
873 {
874 if (!HAL_MVD_InitHW())
875 {
876 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
877 return FALSE;
878 }
879 }
880
881 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
882 {
883 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
884 return FALSE;
885 }
886 }
887
888 #if SUPPORT_G2VP9 && defined(VDEC3)
889 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
890 {
891 if (!HAL_VPU_EX_MVDInUsed())
892 {
893 if (!HAL_MVD_InitHW())
894 {
895 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
896 return FALSE;
897 }
898 }
899 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
900 {
901 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
902 return FALSE;
903 }
904 }
905 #endif
906
907 return TRUE;
908 }
909
_VPU_EX_InClock(MS_U32 u32type)910 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
911 {
912 switch (u32type)
913 {
914 case VPU_CLOCK_240MHZ:
915 return 240000000UL;
916 case VPU_CLOCK_216MHZ:
917 return 216000000UL;
918 case VPU_CLOCK_192MHZ:
919 return 192000000UL;
920 case VPU_CLOCK_12MHZ:
921 return 12000000UL;
922 case VPU_CLOCK_320MHZ:
923 return 320000000UL;
924 case VPU_CLOCK_288MHZ:
925 return 288000000UL;
926 case VPU_CLOCK_432MHZ:
927 return 432000000UL;
928 default:
929 return 384000000UL;
930 }
931 }
932
933
934 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
935 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)936 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
937 {
938 #ifndef MSOS_TYPE_LINUX_KERNEL
939 MS_U8 ClassNum = 0;
940 MBX_Result result;
941
942 if (bVPUMbxInitFlag == TRUE)
943 {
944 return TRUE;
945 }
946
947 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
948 {
949 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
950 return FALSE;
951 }
952 else
953 {
954 MApi_MBX_Enable(TRUE);
955 }
956
957 if (E_MBX_SUCCESS != MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum))
958 {
959 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail\n");
960 return FALSE;
961 }
962
963 result = MApi_MBX_RegisterMSG(ClassNum, 10);
964
965 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
966 {
967 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
968 return FALSE;
969 }
970 else
971 {
972 bVPUMbxInitFlag = TRUE;
973 u8VPUMbxMsgClass = ClassNum;
974 return TRUE;
975 }
976 #else
977 return FALSE;
978 #endif
979 }
980
981 #ifdef MBX_2K
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)982 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
983 {
984 MBX_Result result;
985 MS_U8 u8Index;
986
987 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
988 {
989 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
990 }
991
992 if (bVPUMbxInitFlag == FALSE)
993 {
994 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
995 }
996
997 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
998 VPUReeToTeeMbxMsg.u8Ctrl = 0;
999 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1000 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1001 VPUReeToTeeMbxMsg.u8Index = msg_type;
1002
1003 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1004 if (E_MBX_SUCCESS != result)
1005 {
1006 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1007 }
1008
1009 // Receive Reply ACK from TEE side.
1010 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1011
1012 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1013
1014 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1015 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1016 {
1017 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1018 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1019 }
1020 else
1021 #else
1022 do
1023 {
1024 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1025 } while(E_MBX_SUCCESS != result);
1026 #endif
1027 {
1028 u8Index = VPUTeeToReeMbxMsg.u8Index;
1029 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1030
1031 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1032 {
1033 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1034 }
1035 }
1036
1037 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1038 }
1039 #endif
1040
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1041 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1042 {
1043 #ifdef MBX_2K
1044 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1045 {
1046 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1047 {
1048 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1049 return FALSE;
1050 }
1051 else
1052 {
1053 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1054 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1055 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1056 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1057 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1058 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1059 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1060 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1061
1062 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1063
1064
1065 MS_U32 u32Start;
1066
1067 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1068 {
1069 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1070 pVPUHalContext->u32VPUSHMAddr = u32Start;
1071 }
1072 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1073 {
1074 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1075 pVPUHalContext->u32VPUSHMAddr = u32Start;
1076
1077 }
1078 else // == 0
1079 {
1080 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1081 }
1082 }
1083 }
1084 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1085 {
1086 MS_U32 u32Offset;
1087 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1088 {
1089 u32Offset = u32SHMAddr-u32MIU1Addr;
1090 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1091 }
1092 else
1093 {
1094 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1095 }
1096 }
1097 return true;
1098 #else
1099 return FALSE;
1100 #endif
1101 }
1102
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1103 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1104 {
1105 bVPUMbxInitFlag = TRUE;
1106 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1107 return TRUE;
1108 }
1109
1110 #endif
1111
HAL_VPU_EX_GetFWReload(void)1112 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1113 {
1114 return pVPUHalContext->bVpuExReloadFW;
1115 }
1116
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1117 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1118 {
1119 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1120 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1121 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='0'
1122 && *((MS_U8*)(u32SrcAddr+0x88))=='V' && *((MS_U8*)(u32SrcAddr+0x89))=='D'
1123 && *((MS_U8*)(u32SrcAddr+0x8a))=='E' && *((MS_U8*)(u32SrcAddr+0x8b))=='C'
1124 && *((MS_U8*)(u32SrcAddr+0x8c))=='3' && *((MS_U8*)(u32SrcAddr+0x8d))=='0'
1125 )
1126 {
1127 return FALSE;
1128 }
1129 else
1130 {
1131 return TRUE;
1132 }
1133 }
1134
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1135 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1136 {
1137 MS_PHY u32fwPA = NULL; //physical address
1138 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1139
1140 if (TRUE == HAL_VPU_EX_IsPowered())
1141 {
1142 VPU_MSG_DBG("IsPowered\n");
1143 return TRUE;
1144 }
1145 else
1146 {
1147 //VPU hold
1148 HAL_VPU_EX_SwRst(FALSE);
1149
1150 //VPU clock on
1151 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1152
1153 if (VPU_I_R_ON_MIU0)
1154 VPUInitParams.u8MiuSel = 0;
1155 else if (VPU_I_R_ON_MIU1)
1156 VPUInitParams.u8MiuSel = 1;
1157 else if (VPU_I_R_ON_MIU2)
1158 VPUInitParams.u8MiuSel = 2;
1159
1160 HAL_VPU_EX_Init(&VPUInitParams);
1161 }
1162
1163 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1164 VPU_EX_TaskInfo *pTaskInfo = NULL;
1165 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1166
1167 if (pInitPara)
1168 {
1169 pFWCodeCfg = pInitPara->pFWCodeCfg;
1170 pTaskInfo = pInitPara->pTaskInfo;
1171 pVlcCfg = pInitPara->pVLCCfg;
1172 }
1173 else
1174 {
1175 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1176 return FALSE;
1177 }
1178
1179 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1180 #ifdef MBX_2K
1181 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1182 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1183 {
1184 SYS_TEEINFO teemode;
1185 MDrv_SYS_ReadKernelCmdLine();
1186 MDrv_SYS_GetTEEInfo(&teemode);
1187 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1188 {
1189 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1190
1191 if (FALSE == HAL_VPU_EX_GetFWReload())
1192 {
1193 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1194 {
1195 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1196 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1197 {
1198 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1199 return FALSE;
1200 }
1201 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1202 }
1203 else
1204 {
1205 //Check f/w prefix "VDEC30"
1206 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1207 {
1208 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1209 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1210 {
1211 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1212 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1213 return FALSE;
1214 }
1215 }
1216 else
1217 {
1218 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1219 }
1220 }
1221 }
1222 else
1223 {
1224 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1225 {
1226 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1227 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1228 return FALSE;
1229 }
1230 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1231 }
1232 }
1233 }
1234 else
1235 #endif
1236 #endif
1237 {
1238 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1239
1240 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1241 {
1242 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1243 return FALSE;
1244 }
1245 }
1246
1247 if (pVlcCfg)
1248 {
1249 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1250 {
1251 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1252 return FALSE;
1253 }
1254 }
1255
1256 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1257 {
1258 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1259 return FALSE;
1260 }
1261
1262 //Init HW
1263 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1264 {
1265 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1266 //_MVD_INIT_FAIL_RET();
1267 return FALSE;
1268 }
1269 else
1270 {
1271 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1272 }
1273
1274 //set vpu clock to FW
1275 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1276 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1277
1278 ctl_ptr->statue = CTL_STU_NONE;
1279 //notify controller the interface version of VPU driver.
1280 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1281 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1282 MsOS_FlushMemory();
1283 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1284
1285 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1286 if (TRUE == HAL_VPU_EX_IsRsted())
1287 {
1288 VPU_MSG_DBG("VPU_IsRsted\n");
1289 return TRUE;
1290 }
1291 else
1292 {
1293 HAL_VPU_EX_SwRstRelse();
1294 }
1295
1296 return TRUE;
1297 }
1298
_VPU_EX_DeinitHW(void)1299 static MS_BOOL _VPU_EX_DeinitHW(void)
1300 {
1301 MS_BOOL bRet = FALSE;
1302
1303 if (FALSE == HAL_VPU_EX_MVDInUsed())
1304 {
1305 bRet = HAL_MVD_DeinitHW();
1306 }
1307
1308 if (FALSE == HAL_VPU_EX_HVDInUsed())
1309 {
1310 bRet = HAL_HVD_EX_DeinitHW();
1311 }
1312 #if SUPPORT_G2VP9 && defined(VDEC3)
1313 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1314 {
1315 bRet = HAL_VP9_EX_DeinitHW();
1316 }
1317 #endif
1318 return bRet;
1319 }
1320
_VPU_EX_DeinitAll(void)1321 static MS_BOOL _VPU_EX_DeinitAll(void)
1322 {
1323 HAL_VPU_EX_SwRst(TRUE);
1324 _VPU_EX_DeinitHW();
1325 HAL_VPU_EX_DeInit();
1326
1327 return TRUE;
1328 }
1329
_VPU_EX_GetActiveCodecCnt(void)1330 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1331 {
1332 MS_U32 i;
1333 MS_U8 u8ActiveCnt = 0;
1334 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1335 {
1336 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1337 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1338 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1339 {
1340 u8ActiveCnt++;
1341 }
1342 }
1343 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1344 {
1345 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1346 }
1347 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1348 return u8ActiveCnt;
1349 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1350 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1351 {
1352 if (TRUE)
1353 {
1354 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1355 }
1356 else
1357 {
1358 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1359 }
1360 }
1361
_VPU_EX_ClockSpeed(MS_U32 u32type)1362 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1363 {
1364 switch (u32type)
1365 {
1366 case VPU_CLOCK_240MHZ:
1367 case VPU_CLOCK_216MHZ:
1368 case VPU_CLOCK_192MHZ:
1369 case VPU_CLOCK_12MHZ:
1370 case VPU_CLOCK_320MHZ:
1371 case VPU_CLOCK_288MHZ:
1372 case VPU_CLOCK_384MHZ:
1373 case VPU_CLOCK_432MHZ:
1374 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1375 break;
1376 default:
1377 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1378 break;
1379 }
1380 }
1381 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1382 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1383 {
1384 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1385 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1386 {
1387 return TRUE;
1388 }
1389 return FALSE;
1390 }
1391 #endif
1392
1393
1394 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1395 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1396 {
1397 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1398 {
1399 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1400 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1401 ms_VDECDecompressDeInit();
1402 return TRUE;
1403 }
1404 else
1405 {
1406 return FALSE;
1407 }
1408 }
1409 #endif
1410
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1411 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1412 {
1413 MS_BOOL bRet = TRUE;
1414 pVPUHalContext->_bVPUSingleMode = bEnable;
1415 return bRet;
1416 }
1417
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1418 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1419 {
1420 MS_BOOL bRet = TRUE;
1421 MS_U8 i=0;
1422 if (pstCfg != NULL)
1423 {
1424 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1425 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1426 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1427 {
1428 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1429 }
1430 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1431 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1432 }
1433 else
1434 {
1435 bRet = FALSE;
1436 }
1437 return bRet;
1438 }
1439
1440 //static MS_BOOL bVpuExReloadFW = TRUE;
1441 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1442 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1443 {
1444 pVPUHalContext->bVpuExReloadFW = bReload;
1445 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1446 return TRUE;
1447 }
1448
1449
1450 //-------------------------------------------------------------------------------------------------
1451 // Global Functions
1452 //-------------------------------------------------------------------------------------------------
1453 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1454 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1455 {
1456 #if HVD_ENABLE_RV_FEATURE
1457 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1458 {
1459 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1460 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1461 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1462
1463 if (pVlcCfg->u32BinSize)
1464 {
1465 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1466
1467 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1468 {
1469 cpyflag = E_SPIDMA_DEV_MIU1;
1470 }
1471 else
1472 {
1473 cpyflag = E_SPIDMA_DEV_MIU0;
1474 }
1475
1476 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1477 {
1478 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1479 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1480
1481 return FALSE;
1482 }
1483 }
1484 else
1485 {
1486 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1487 return FALSE;
1488 }
1489 #else
1490 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1491 return FALSE;
1492 #endif
1493 }
1494 else
1495 {
1496 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1497 {
1498 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1499 {
1500 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1501 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1502
1503 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1504 BDMA_Result bdmaRlt;
1505
1506 MsOS_FlushMemory();
1507 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1508
1509 if (E_BDMA_OK != bdmaRlt)
1510 {
1511 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1512 }
1513 #else
1514 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1515 #endif
1516 }
1517 else
1518 {
1519 VPU_MSG_ERR
1520 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1521 return FALSE;
1522 }
1523 }
1524 else
1525 {
1526 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1527 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1528 MS_U8 *pu8HVD_VLC_Binary;
1529
1530 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1531
1532 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1533 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1534 (MS_U32) sizeof(u8HVD_VLC_Binary));
1535
1536 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1537 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1538 #else
1539 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1540 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1541 (MS_U32) sizeof(u8HVD_VLC_Binary));
1542
1543 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1544 #endif
1545 #else
1546 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1547 return FALSE;
1548 #endif
1549 }
1550 }
1551 #endif
1552
1553 return TRUE;
1554 }
1555 #endif
1556 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1557 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1558 #else
1559 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1560 #endif
1561 {
1562 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1563 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1564 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1565 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1566 MS_U32 u32Arg = 0xFFFFFFFF;
1567 MS_U32 u32Timeout = 0;
1568 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1569 MS_U32 u32CmdArg = 0;
1570 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1571 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1572
1573 _HAL_VPU_Entry();
1574 //Check FW buffer size
1575 if (1 == u8Offset)
1576 {
1577 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1578 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1579
1580 if (u32CurFWBuffSize < u32MinFWBuffSize)
1581 {
1582 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1583 _HAL_VPU_Release();
1584 return FALSE;
1585 }
1586 }
1587
1588 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1589 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1590 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1591 {
1592 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1593 }
1594 #ifdef VDEC3
1595 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1596 #endif
1597
1598 if (0 == pVPUHalContext->u8TaskCnt)
1599 {
1600 //No task is created, need to load f/w, etc.
1601 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1602
1603 if (!_VPU_EX_InitAll(pInitPara))
1604 {
1605 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1606 _HAL_VPU_Release();
1607 return FALSE;
1608 }
1609
1610 //Check if controller finish initialization: clear mailbox, etc.
1611 //Need to check it before sending any controller commands!
1612 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1613 while (CTL_STU_NONE == ctl_ptr->statue)
1614 {
1615 if (HVD_GetSysTime_ms() > u32Timeout)
1616 {
1617 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1618 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1619 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1620 MS_U32 t=0;
1621 for (t=0; t<30; t++)
1622 {
1623 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1624 }
1625 _HAL_VPU_Release();
1626 return FALSE;
1627 }
1628
1629 MsOS_ReadMemory();
1630 }
1631
1632 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1633 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1634
1635 }
1636 else
1637 {
1638 if (pVPUHalContext->_bVPUSingleMode)
1639 {
1640 //Show error message
1641 printf("This task will use dram instead of sram!!!\n");
1642 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1643 }
1644
1645 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1646 {
1647 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1648 _HAL_VPU_Release();
1649 return FALSE;
1650 }
1651 if (pInitPara->pVLCCfg)
1652 {
1653 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1654 {
1655 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1656 _HAL_VPU_Release();
1657 return FALSE;
1658 }
1659 }
1660 }
1661
1662
1663 #ifdef VDEC3
1664 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1665 {
1666 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1667
1668 memset(pTemp4,0,sizeof(VDEC_VBBU));
1669
1670 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1671
1672 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1673
1674 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1675
1676 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1677
1678 memset(pTemp2,0,sizeof(CMD_QUEUE));
1679
1680 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1681
1682 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1683
1684 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1685
1686 memset(pTemp3,0,0x2000);
1687
1688 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1689
1690 memset((void*)pVersion,0,0x8);
1691
1692 *pVersion = 1; //0:diu, 1:wb
1693 }
1694
1695 #endif
1696
1697 #if 1 // For TEE
1698 #ifdef VDEC3
1699 #if SUPPORT_G2VP9
1700 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1701 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1702 #else
1703 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1704 #endif
1705 #else
1706 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1707 #endif
1708 {
1709 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1710
1711 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1712 {
1713 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1714 }
1715 else
1716 {
1717 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1718 }
1719
1720 MsOS_FlushMemory();
1721 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1722
1723 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1724 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1725 }
1726 #endif
1727
1728 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1729 {
1730 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1731 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1732
1733 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1734
1735 MsOS_FlushMemory();
1736 }
1737
1738 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1739 {
1740 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1741 //arg=1 to get better performance for single task
1742 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1743 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1744 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1745 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1746 {
1747 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1748 }
1749 }
1750 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1751 {
1752 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1753 {
1754 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1755 {
1756 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1757 u32CmdArg = CTL_MODE_3DTV;
1758 break;
1759 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1760 u32CmdArg = CTL_MODE_3DTV_PROG;
1761 break;
1762 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1763 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1764 break;
1765 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1766 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1767 break;
1768 default:
1769 u32CmdArg = CTL_MODE_3DTV;
1770 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1771 break;
1772 }
1773 }
1774 else
1775 {
1776 u32CmdArg = CTL_MODE_3DWMV;
1777 }
1778 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1779 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1780 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1781 {
1782 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1783 }
1784 }
1785 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1786 {
1787 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1788 {
1789 u32CmdArg = CTL_MODE_ONE_STC;
1790 }
1791 else
1792 {
1793 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1794 }
1795 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1796 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1797 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1798 {
1799 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1800 }
1801 }
1802
1803 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1804 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1805 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1806 #ifdef VDEC3
1807 {
1808 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1809 }
1810 #else
1811 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1812 #endif
1813
1814 #ifdef VDEC3
1815 #if SUPPORT_G2VP9
1816 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1817 #else
1818 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1819 #endif
1820 {
1821 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1822 }
1823 #else
1824 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1825 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1826 #endif
1827 else
1828 {
1829 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1830 _HAL_VPU_Release();
1831 return FALSE;
1832 }
1833 #else
1834 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1835 #endif
1836 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1837
1838 MsOS_ReadMemory();
1839 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1840 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1841
1842 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1843 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1844 {
1845 if (HVD_GetSysTime_ms() > u32Timeout)
1846 {
1847 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1848 MS_U32 t=0;
1849 for (t=0; t<30; t++)
1850 {
1851 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1852 }
1853 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1854 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1855 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1856 _HAL_VPU_Release();
1857 return FALSE;
1858 //#endif
1859 }
1860
1861 MsOS_ReadMemory();
1862 }
1863
1864 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1865 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1866
1867 #ifdef VDEC3
1868 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1869 #else
1870 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1871 #endif
1872 {
1873 HAL_HVD_EX_SetBufferAddr(u32Id);
1874 }
1875
1876 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1877 {
1878 eDecType = E_VPU_EX_DECODER_MVD;
1879 }
1880 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1881 {
1882 eDecType = E_VPU_EX_DECODER_HVD;
1883 }
1884 #ifdef VDEC3
1885 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1886 {
1887 eDecType = E_VPU_EX_DECODER_EVD;
1888 }
1889 #if SUPPORT_G2VP9
1890 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1891 {
1892 eDecType = E_VPU_EX_DECODER_G2VP9;
1893 }
1894 #endif
1895 #endif
1896 else
1897 {
1898 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1899 _HAL_VPU_Release();
1900 return FALSE;
1901 }
1902
1903 #ifdef VDEC3
1904 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1905 {
1906 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1907 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1908 }
1909 #endif
1910
1911 if (pTaskInfo->eDecType != eDecType)
1912 {
1913 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1914 pTaskInfo->eDecType, eDecType);
1915 }
1916 goto _SAVE_DEC_TYPE;
1917
1918 _SAVE_DEC_TYPE:
1919 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1920 {
1921 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1922 }
1923 else
1924 {
1925 VPU_MSG_ERR("Cannot save eDecType!!\n");
1926 }
1927
1928 (pVPUHalContext->u8TaskCnt)++;
1929 _HAL_VPU_Release();
1930 return TRUE;
1931 }
1932
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1933 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1934 {
1935 HVD_Return eRet;
1936 #ifdef VDEC3
1937 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
1938 #else
1939 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
1940 #endif
1941 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1942 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
1943
1944 _HAL_VPU_Entry();
1945 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
1946
1947 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
1948 if(eRet != E_HVD_RETURN_SUCCESS)
1949 {
1950 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
1951 }
1952
1953 {
1954 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1955 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1956 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1957
1958 MsOS_ReadMemory();
1959
1960 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1961 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1962
1963 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
1964 {
1965 if (HVD_GetSysTime_ms() > u32Timeout)
1966 {
1967 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
1968 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1969 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
1970
1971 if(pVPUHalContext->u8TaskCnt == 1)
1972 {
1973 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
1974 break;
1975 }
1976 else if(pVPUHalContext->u8TaskCnt == 2)
1977 {
1978 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
1979 break;
1980 }
1981 else
1982 {
1983 VPU_MSG_ERR("Task number is not correct\n");
1984 _HAL_VPU_Release();
1985 return FALSE;
1986 }
1987 }
1988
1989 MsOS_ReadMemory();
1990 }
1991
1992 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1993 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1994 }
1995
1996 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
1997 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
1998 {
1999 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2000 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2001 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2002 }
2003
2004 if (pVPUHalContext->u8TaskCnt)
2005 {
2006 (pVPUHalContext->u8TaskCnt)--;
2007 }
2008 else
2009 {
2010 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2011 }
2012
2013 if (0 == pVPUHalContext->u8TaskCnt)
2014 {
2015 int i;
2016 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2017 _VPU_EX_DeinitAll();
2018 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2019 pVPUHalContext->u32VPUSHMAddr = 0;
2020
2021 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2022 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2023 }
2024 else
2025 {
2026 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2027 _VPU_EX_DeinitHW();
2028 }
2029
2030 _HAL_VPU_Release();
2031 return TRUE;
2032 }
2033
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2034 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2035 {
2036 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2037 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2038 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2039 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2040 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2041 #endif
2042
2043 if (FALSE == HAL_VPU_EX_GetFWReload())
2044 {
2045 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2046 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2047 {
2048 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2049 }
2050 else
2051 {
2052 //Check f/w prefix "VDEC30"
2053 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2054 {
2055 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2056 }
2057 else
2058 {
2059 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2060 return TRUE;
2061 }
2062 }
2063 }
2064
2065 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2066 {
2067 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2068 if (u32Size != 0)
2069 {
2070 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2071
2072
2073 MS_U32 u32Start;
2074 MS_U32 u32StartOffset;
2075 MS_U8 u8MiuSel;
2076
2077 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2078
2079
2080 if(u8MiuSel == E_CHIP_MIU_0)
2081 cpyflag = E_SPIDMA_DEV_MIU0;
2082 else if(u8MiuSel == E_CHIP_MIU_1)
2083 cpyflag = E_SPIDMA_DEV_MIU1;
2084 else if(u8MiuSel == E_CHIP_MIU_2)
2085 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2086
2087 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2088 {
2089 goto _load_code_fail;
2090 }
2091 }
2092 else
2093 {
2094 goto _load_code_fail;
2095 }
2096 #else
2097 goto _load_code_fail;
2098 #endif
2099 }
2100 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2101 {
2102 if (u32BinAddr != 0 && u32Size != 0)
2103 {
2104 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2105 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2106 {
2107 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2108 {
2109 VPU_MSG_INFO("Decompress ok!!!\n");
2110 }
2111 else
2112 {
2113 VPU_MSG_INFO("Decompress fail!!!\n");
2114 }
2115 }
2116 else
2117 #endif
2118 {
2119 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2120 }
2121 }
2122 else
2123 {
2124 goto _load_code_fail;
2125 }
2126 }
2127 else
2128 {
2129 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2130 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2131 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2132 (MS_U32) sizeof(u8HVD_FW_Binary));
2133
2134 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2135 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2136 {
2137 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2138 {
2139 VPU_MSG_INFO("Decompress ok!!!\n");
2140 }
2141 else
2142 {
2143 VPU_MSG_INFO("Decompress fail!!!\n");
2144 }
2145 }
2146 else
2147 #endif
2148 {
2149 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2150 }
2151 #else
2152 goto _load_code_fail;
2153 #endif
2154 }
2155
2156 MAsm_CPU_Sync();
2157 MsOS_FlushMemory();
2158
2159 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2160 {
2161 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2162 goto _load_code_fail;
2163 }
2164
2165 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2166 return TRUE;
2167
2168 _load_code_fail:
2169 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2170 return FALSE;
2171 }
2172
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2173 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2174 {
2175 u32VPURegOSBase = u32RegBase;
2176 }
2177
HAL_VPU_EX_Init_Share_Mem(void)2178 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2179 {
2180 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2181
2182 MS_U32 u32ShmId;
2183 MS_VIRT u32Addr;
2184 MS_U32 u32BufSize;
2185
2186
2187 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2188 sizeof(VPU_Hal_CTX),
2189 &u32ShmId,
2190 &u32Addr,
2191 &u32BufSize,
2192 MSOS_SHM_QUERY))
2193 {
2194 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2195 sizeof(VPU_Hal_CTX),
2196 &u32ShmId,
2197 &u32Addr,
2198 &u32BufSize,
2199 MSOS_SHM_CREATE))
2200 {
2201 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2202 if(pVPUHalContext == NULL)
2203 {
2204 pVPUHalContext = &gVPUHalContext;
2205 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2206 _VPU_EX_Context_Init();
2207 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2208 }
2209 else
2210 {
2211 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2212 }
2213 //return FALSE;
2214 }
2215 else
2216 {
2217 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2218 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2219 _VPU_EX_Context_Init();
2220 }
2221 }
2222 else
2223 {
2224 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2225 }
2226 #else
2227 if(pVPUHalContext == NULL)
2228 {
2229 pVPUHalContext = &gVPUHalContext;
2230 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2231 _VPU_EX_Context_Init();
2232 }
2233 #endif
2234
2235 return TRUE;
2236
2237 }
2238
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2239 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2240 {
2241 MS_U32 i = 0;
2242
2243 _HAL_VPU_MutexCreate();
2244
2245 _HAL_VPU_Entry();
2246
2247 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2248 {
2249 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2250 {
2251 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2252 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2253 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2254 _HAL_VPU_Release();
2255 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2256 }
2257 }
2258 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2259 {
2260 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2261 {
2262 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2263 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2264 {
2265 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2266 _HAL_VPU_Release();
2267 return pVPUHalContext->_stVPUStream[i].eStreamId;
2268 }
2269 }
2270 }
2271 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2272 {
2273 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2274 {
2275 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2276 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2277 {
2278 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2279 _HAL_VPU_Release();
2280 return pVPUHalContext->_stVPUStream[i].eStreamId;
2281 }
2282 }
2283 }
2284 #ifdef VDEC3
2285 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2286 {
2287 #if 1 // bound FW task to main/sub stream
2288 i = eStreamType - E_HAL_VPU_N_STREAM;
2289 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2290 {
2291 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2292 _HAL_VPU_Release();
2293 return pVPUHalContext->_stVPUStream[i].eStreamId;
2294 }
2295 #else // dynamic select FW task id
2296 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2297 {
2298 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2299 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2300 {
2301 return pVPUHalContext->_stVPUStream[i].eStreamId;
2302 }
2303 }
2304 #endif
2305 }
2306 #endif
2307
2308 _HAL_VPU_Release();
2309
2310 return E_HAL_VPU_STREAM_NONE;
2311 }
2312
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2313 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2314 {
2315 if(u8Idx > 2)
2316 {
2317 return FALSE;
2318 }
2319
2320 _HAL_VPU_Entry();
2321
2322 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2323 {
2324 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2325 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2326 }
2327 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2328 {
2329 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2330 }
2331
2332 _HAL_VPU_Release();
2333
2334 return TRUE;
2335 }
2336
HAL_VPU_EX_CheckFreeStream(void)2337 MS_U8 HAL_VPU_EX_CheckFreeStream(void)
2338 {
2339 MS_U8 u8Idx = 0;
2340
2341 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2342 {
2343 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2344 break;
2345 }
2346
2347 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2348 {
2349 VPU_MSG_ERR("all vpu free streams are occupied \n");
2350 return -1;
2351 }
2352
2353 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2354 return u8Idx;
2355 }
2356
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2357 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2358 {
2359 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2360
2361 // enable module
2362 _VPU_EX_ClockInv(InitParams->bClockInv);
2363 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2364 HAL_VPU_EX_PowerCtrl(TRUE);
2365
2366 #if 1 //Create VPU's own mutex
2367 //_HAL_VPU_MutexCreate();
2368 #else
2369 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2370 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2371 #endif
2372
2373 return TRUE;
2374 }
2375
HAL_VPU_EX_DeInit(void)2376 MS_BOOL HAL_VPU_EX_DeInit(void)
2377 {
2378 if (0 != _VPU_EX_GetActiveCodecCnt())
2379 {
2380 VPU_MSG_DBG("do nothing since codec is active.\n");
2381 return TRUE;
2382 }
2383
2384 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2385
2386 HAL_VPU_EX_PowerCtrl(FALSE);
2387 HAL_VPU_EX_SwRelseMAU();
2388 //_HAL_VPU_MutexDelete();
2389
2390 return TRUE;
2391 }
2392
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2393 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2394 {
2395 if (bEnable)
2396 {
2397 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2398 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2399 pVPUHalContext->_bVPUPowered = TRUE;
2400 }
2401 else
2402 {
2403 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2404 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2405 pVPUHalContext->_bVPUPowered = FALSE;
2406 }
2407 }
2408
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2409 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2410 {
2411 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2412 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2413 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2414 VPU_EX_TimerDelayMS(1);
2415 }
2416
2417 ///-----------------------------------------------------------------------------
2418 /// config AVCH264 CPU
2419 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2420 /// @param u8dlend_en \b IN: endian
2421 /// - 1, little endian
2422 /// - 0, big endian
2423 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2424 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2425 {
2426 MS_BOOL bRet = TRUE;
2427 MS_U32 u32Offset = 0;
2428 MS_U16 tempreg = 0;
2429 MS_U8 u8MiuSel;
2430 //MS_U32 u32TmpStartOffset;
2431
2432 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2433
2434 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2435 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2436 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2437 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2438 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2439 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2440 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2441 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2442 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2443 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2444
2445 #if (HVD_ENABLE_IQMEM)
2446 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2447 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2448 #endif
2449
2450 #if (VPU_FORCE_MIU_MODE)
2451 // Data sram base Unit: byte address
2452 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2453 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2454 // Instruction sram base Unit: byte address
2455 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2456 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2457
2458 #ifndef HAL_FEATURE_MAU
2459 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2460 #endif
2461 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2462
2463 //use force miu mode
2464 if(u8MiuSel == E_CHIP_MIU_0)
2465 {
2466 #ifdef HAL_FEATURE_MAU
2467 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2468 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2469 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2470 #else
2471 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2472 #endif
2473 }
2474 else if(u8MiuSel == E_CHIP_MIU_1)
2475 {
2476 #ifdef HAL_FEATURE_MAU
2477 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2478 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2479 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2480 #else
2481 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2482 #endif
2483 }
2484 else //miu 2
2485 {
2486 #ifdef HAL_FEATURE_MAU
2487 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2488 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2489 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2490 #else
2491 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2492 #endif
2493 }
2494 #else
2495 ///TODO:
2496 #endif
2497
2498
2499 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2500 tempreg |= VPU_REG_IO2_EN;
2501 tempreg |= VPU_REG_QMEM_SPACE_EN;
2502 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2503
2504 return bRet;
2505 }
2506
2507 ///-----------------------------------------------------------------------------
2508 /// Set IQMem data access mode or instruction fetch mode
2509 /// @param u8dlend_en \b IN: endian
2510 /// - 1, switch to data access mode
2511 /// - 0, switch to instruction fetch mode
2512 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2513 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2514 {
2515
2516 if(bEnable){
2517
2518 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2519 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2520
2521 }
2522 else{
2523
2524 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2525
2526 }
2527 }
2528
2529 ///-----------------------------------------------------------------------------
2530 /// H.264 SW reset
2531 /// @return TRUE or FALSE
2532 /// - TRUE, Success
2533 /// - FALSE, Failed
2534 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2535 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2536 {
2537 MS_U16 tempreg = 0, tempreg1 = 0;
2538
2539 // stall R2
2540 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2541 tempreg |= VPU_REG_CPU_STALL_EN;
2542 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2543
2544 // write R2 RIU registers to select DCU/ICU debug data
2545 // Writing these registers here provides enough time for them to
2546 // take effect.
2547 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2548 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2549 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2550 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2551
2552 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2553 // This step is important because in the next step we want to make
2554 // sure "DCU is not replaying when R2 is stalled".
2555 int idle_cnt = 100;
2556 do
2557 {
2558 if (--idle_cnt == 0)
2559 {
2560 printf("VPU_REG_CPU_STALL_EN is not set\n");
2561 break;
2562 }
2563 MsOS_DelayTaskUs(1000);
2564 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2565
2566 // check CPU status: DCU should NOT be replaying
2567 // If R2 has been stalled, we can guarantee that if we found DCU is
2568 // NOT replaying, it will NOT replay later even CPU is going to issue
2569 // a load/store instruction.
2570 idle_cnt = 100;
2571 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2572 {
2573 if (--idle_cnt == 0)
2574 {
2575 printf("DCU is replaying\n");
2576 break;
2577 }
2578 MsOS_DelayTaskUs(1000);
2579 }
2580
2581 // wait 1ms to prevent race condition between (1) DCU is not
2582 // replaying, and (2) BIU start to doing new job or ICU start to
2583 // fetch new instruction
2584 MsOS_DelayTaskUs(1000);
2585
2586 // check BIU should be empty
2587 idle_cnt = 100;
2588 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2589 {
2590 if (--idle_cnt == 0)
2591 {
2592 printf("BIU DCU idle time out~~~~~\n");
2593 break;
2594 }
2595 MsOS_DelayTaskUs(1000);
2596 }
2597
2598 // check CPU is not requesting ICU
2599 idle_cnt = 100;
2600 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2601 {
2602 if (--idle_cnt == 0)
2603 {
2604 printf("CPU keeps requesting ICU\n");
2605 break;
2606 }
2607 MsOS_DelayTaskUs(1000);
2608 }
2609
2610 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2611 // (2) ISB start to fetch
2612 MsOS_DelayTaskUs(1000);
2613
2614 // check ISB should be idle
2615 idle_cnt = 100;
2616 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2617 {
2618 if (--idle_cnt == 0)
2619 {
2620 printf("ISB is busy\n");
2621 break;
2622 }
2623 MsOS_DelayTaskUs(1000);
2624 }
2625
2626 #ifdef HAL_FEATURE_MAU
2627 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2628 if (bCheckMauIdle)
2629 {
2630 MS_U32 mau_idle_cnt = 100;// ms
2631 while (mau_idle_cnt)
2632 {
2633 if (TRUE == _VPU_EX_MAU_IDLE())
2634 {
2635 break;
2636 }
2637 mau_idle_cnt--;
2638 MsOS_DelayTaskUs(1000);
2639 }
2640
2641 if (mau_idle_cnt == 0)
2642 {
2643 printf("MAU idle time out~~~~~\n");
2644 }
2645 }
2646 #endif
2647
2648 // this command set MIU to block R2 (does not ack R2's request)
2649 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2650
2651 #ifdef HAL_FEATURE_MAU
2652 // reset MAU
2653 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2654 tempreg1 |= MAU1_REG_SW_RESET;
2655 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2656 #if defined(UDMA_FPGA_ENVI)
2657 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2658 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2659 #endif
2660 #endif
2661
2662 // reset R2
2663 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2664 // by the same RIU write, the R2 reset signal may reach afifo eralier
2665 // than MIU reset and afifo write pointer will be reset to position 0.
2666 // In this case, afifo consider it is not empty because read/write
2667 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2668 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2669 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2670 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2671 VPU_EX_TimerDelayMS(1);
2672 tempreg &= ~VPU_REG_CPU_R2_EN;
2673 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2674 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2675
2676 VPU_EX_TimerDelayMS(1);
2677
2678 // this command set MIU to accept R2 (can ack R2's request)
2679 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2680
2681 pVPUHalContext->_bVPURsted = FALSE;
2682 return TRUE;
2683 }
2684 /*
2685 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2686 {
2687 MS_U16 tempreg = 0, tempreg1 = 0;
2688 #ifndef HAL_FEATURE_MAU
2689 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2690 tempreg |= VPU_REG_CPU_STALL_EN;
2691 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2692
2693 MS_U32 idle_cnt = 100;// ms
2694 while (idle_cnt)
2695 {
2696 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2697 {
2698 break;
2699 }
2700 idle_cnt--;
2701 MsOS_DelayTask(1);
2702 }
2703
2704 if (idle_cnt == 0)
2705 {
2706 printf("ISB ICU idle time out~~~~~\n");
2707 }
2708
2709 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2710 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2711 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2712 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2713
2714 MS_U32 idle_cnt_1 = 100;// ms
2715 while (idle_cnt_1)
2716 {
2717 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2718 {
2719 break;
2720 }
2721 idle_cnt_1--;
2722 MsOS_DelayTask(1);
2723 }
2724
2725 if (idle_cnt_1 == 0)
2726 {
2727 printf("BIU DCU idle time out~~~~~\n");
2728 }
2729
2730 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2731 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2732 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2733 VPU_EX_TimerDelayMS(1);
2734 tempreg &= ~VPU_REG_CPU_R2_EN;
2735 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2736 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2737
2738 #else
2739 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2740
2741 if (bCheckMauIdle)
2742 {
2743 MS_U32 mau_idle_cnt = 100;// ms
2744 while (mau_idle_cnt)
2745 {
2746 if (TRUE == _VPU_EX_MAU_IDLE())
2747 {
2748 break;
2749 }
2750 mau_idle_cnt--;
2751 MsOS_DelayTask(1);
2752 }
2753
2754 if (mau_idle_cnt == 0)
2755 {
2756 printf("MAU idle time out~~~~~\n");
2757 }
2758 }
2759
2760
2761 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2762
2763 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2764 tempreg1 |= MAU1_REG_SW_RESET;
2765 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2766
2767 #if defined(UDMA_FPGA_ENVI)
2768 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2769 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2770 #endif
2771
2772 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2773 tempreg &= ~VPU_REG_CPU_R2_EN;
2774 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2775 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2776 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2777 #endif
2778 VPU_EX_TimerDelayMS(1);
2779 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2780
2781 pVPUHalContext->_bVPURsted = FALSE;
2782 return TRUE;
2783 }
2784 */
2785 ///-----------------------------------------------------------------------------
2786 /// CPU reset release
2787 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2788 void HAL_VPU_EX_SwRstRelse(void)
2789 {
2790 MS_U16 tempreg = 0;
2791
2792 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2793 tempreg &= ~VPU_REG_CPU_STALL_EN;
2794 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2795
2796 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2797 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2798 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2799 VPU_EX_TimerDelayMS(1);
2800 tempreg |= VPU_REG_CPU_SW_RSTZ;
2801 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2802 VPU_EX_TimerDelayMS(1);
2803 tempreg |= VPU_REG_CPU_R2_EN;
2804 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2805 #ifdef HAL_FEATURE_MAU
2806 MS_U16 tempreg1 = 0;
2807 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2808 tempreg1 &= ~MAU1_REG_SW_RESET;
2809 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2810 #endif
2811 pVPUHalContext->_bVPURsted = TRUE;
2812 }
2813
HAL_VPU_EX_SwRelseMAU(void)2814 void HAL_VPU_EX_SwRelseMAU(void)
2815 {
2816 #ifdef HAL_FEATURE_MAU
2817 MS_U16 tempreg = 0;
2818 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2819 tempreg &= ~MAU1_REG_SW_RESET;
2820 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2821 #endif
2822 }
2823
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2824 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2825 {
2826 MS_U32 u32value = 0;
2827
2828 return u32value;
2829 }
2830
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2831 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2832 {
2833 MS_BOOL bRet = TRUE;
2834
2835 return bRet;
2836 }
2837
2838 ///-----------------------------------------------------------------------------
2839 /// Check AVCH264 Ready or not
2840 /// @return TRUE or FALSE
2841 /// - TRUE, MailBox is free
2842 /// - FALSE, MailBox is busy
2843 /// @param u8MBox \b IN: MailBox to check
2844 /// - AVCH264_HI_MBOX0,
2845 /// - AVCH264_HI_MBOX1,
2846 /// - AVCH264_RISC_MBOX0,
2847 /// - AVCH264_RISC_MBOX1,
2848 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2849 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2850 {
2851 MS_BOOL bResult = FALSE;
2852
2853 switch (u32type)
2854 {
2855 case VPU_HI_MBOX0:
2856 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2857 break;
2858 case VPU_HI_MBOX1:
2859 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2860 break;
2861 case VPU_RISC_MBOX0:
2862 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2863 break;
2864 case VPU_RISC_MBOX1:
2865 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2866 break;
2867 default:
2868 break;
2869 }
2870 return bResult;
2871 }
2872
2873
2874 ///-----------------------------------------------------------------------------
2875 /// Read message from AVCH264
2876 /// @return TRUE or FALSE
2877 /// - TRUE, success
2878 /// - FALSE, failed
2879 /// @param u8MBox \b IN: MailBox to read
2880 /// - AVCH264_RISC_MBOX0
2881 /// - AVCH264_RISC_MBOX1
2882 /// @param u32Msg \b OUT: message read
2883 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2884 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2885 {
2886 MS_BOOL bResult = TRUE;
2887
2888 switch (u32type)
2889 {
2890 case VPU_HI_MBOX0:
2891 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
2892 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
2893 break;
2894 case VPU_HI_MBOX1:
2895 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
2896 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
2897 break;
2898 case VPU_RISC_MBOX0:
2899 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
2900 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
2901 break;
2902 case VPU_RISC_MBOX1:
2903 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
2904 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
2905 break;
2906 default:
2907 *u32Msg = 0;
2908 bResult = FALSE;
2909 break;
2910 }
2911 return bResult;
2912 }
2913
2914 ///-----------------------------------------------------------------------------
2915 /// Mailbox from AVCH264 clear bit resest
2916 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)2917 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
2918 {
2919 switch (u32type)
2920 {
2921 case VPU_RISC_MBOX0:
2922 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
2923 break;
2924 case VPU_RISC_MBOX1:
2925 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
2926 break;
2927 default:
2928 break;
2929 }
2930 }
2931
2932 ///-----------------------------------------------------------------------------
2933 /// Send message to AVCH264
2934 /// @return TRUE or FALSE
2935 /// - TRUE, Success
2936 /// - FALSE, Failed
2937 /// @param u8MBox \b IN: MailBox
2938 /// - AVCH264_HI_MBOX0,
2939 /// - AVCH264_HI_MBOX1,
2940 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)2941 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
2942 {
2943 MS_BOOL bResult = TRUE;
2944
2945 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
2946
2947 switch (u32type)
2948 {
2949 case VPU_HI_MBOX0:
2950 {
2951 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
2952 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
2953 break;
2954 }
2955 case VPU_HI_MBOX1:
2956 {
2957 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
2958 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
2959 break;
2960 }
2961 default:
2962 {
2963 bResult = FALSE;
2964 break;
2965 }
2966 }
2967
2968 return bResult;
2969 }
2970
HAL_VPU_EX_GetProgCnt(void)2971 MS_U32 HAL_VPU_EX_GetProgCnt(void)
2972 {
2973
2974 MS_U16 expc_l=0;
2975 MS_U16 expc_h=0;
2976 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
2977 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
2978 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
2979 }
2980
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)2981 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
2982 {
2983 return _VPU_EX_GetOffsetIdx(u32Id);
2984 }
2985
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)2986 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
2987 {
2988 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2989
2990 if (u32ShmAddr == 0)
2991 {
2992 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
2993 }
2994 else
2995 {
2996 if (u8Offset == 0)
2997 {
2998 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
2999 }
3000 else if (u8Offset == 1)
3001 {
3002 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3003 }
3004 }
3005
3006 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3007 return;
3008 }
3009
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3010 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3011 {
3012 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3013
3014 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3015 }
3016
3017
HAL_VPU_EX_IsPowered(void)3018 MS_BOOL HAL_VPU_EX_IsPowered(void)
3019 {
3020 return pVPUHalContext->_bVPUPowered;
3021 }
3022
HAL_VPU_EX_IsRsted(void)3023 MS_BOOL HAL_VPU_EX_IsRsted(void)
3024 {
3025 return pVPUHalContext->_bVPURsted;
3026 }
3027
HAL_VPU_EX_IsEVDR2(void)3028 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3029 {
3030 #ifdef EVDR2
3031 return TRUE;
3032 #else
3033 return FALSE;
3034 #endif
3035 }
3036
HAL_VPU_EX_MVDInUsed(void)3037 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3038 {
3039 //MVD is in used for MVD or HVD_TSP mode.
3040 MS_U8 i;
3041 MS_U8 u8UseCnt = 0;
3042
3043 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3044 {
3045 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3046 #ifdef VDEC3
3047 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3048 #endif
3049 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3050 {
3051 u8UseCnt++;
3052 }
3053 }
3054
3055 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3056
3057 if (u8UseCnt != 0)
3058 {
3059 return TRUE;
3060 }
3061 else
3062 {
3063 return FALSE;
3064 }
3065 }
3066
HAL_VPU_EX_HVDInUsed(void)3067 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3068 {
3069 //HVD is in used for HVD or MVD in sub stream.
3070 MS_U8 i;
3071 MS_U8 u8UseCnt = 0;
3072 MS_BOOL bMVDTriggerHVD = FALSE;
3073 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3074 {
3075 #ifdef VDEC3
3076 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
3077 (pVPUHalContext->u8HALId[i] == 1) &&
3078 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
3079 #else
3080 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
3081 (E_HAL_VPU_SUB_STREAM0 == pVPUHalContext->_stVPUStream[i].eStreamId) &&
3082 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
3083 #endif
3084
3085 if(bMVDTriggerHVD)
3086 {
3087 VPU_MSG_DBG("%s i:%d eDecodertype:%d u8DecMod:%d\n",__FUNCTION__,i,pVPUHalContext->_stVPUStream[i].eDecodertype,pVPUHalContext->_stVPUDecMode.u8DecMod);
3088 }
3089
3090 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3091 #ifdef VDEC3
3092 ||(E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3093 #endif
3094 ||(TRUE == bMVDTriggerHVD)
3095 )
3096 {
3097 u8UseCnt++;
3098 }
3099 }
3100
3101 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3102
3103 if (u8UseCnt != 0)
3104 {
3105 return TRUE;
3106 }
3107 else
3108 {
3109 return FALSE;
3110 }
3111 }
3112
3113 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3114 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3115 {
3116 MS_U8 i;
3117 MS_U8 u8UseCnt = 0;
3118
3119 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3120 {
3121 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3122 {
3123 u8UseCnt++;
3124 }
3125 }
3126
3127 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3128
3129 if (u8UseCnt != 0)
3130 {
3131 return TRUE;
3132 }
3133 else
3134 {
3135 return FALSE;
3136 }
3137 }
3138
3139 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3140 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3141 {
3142 MS_U8 i;
3143 MS_U8 u8UseCnt = 0;
3144
3145 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3146 {
3147 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3148 {
3149 u8UseCnt++;
3150 }
3151 }
3152
3153 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3154
3155 if (u8UseCnt != 0)
3156 {
3157 return TRUE;
3158 }
3159 else
3160 {
3161 return FALSE;
3162 }
3163 }
3164 #endif
3165 #endif
3166
3167 //-----------------------------------------------------------------------------
3168 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3169 /// @brief \b Function \b Description: Set debug level
3170 /// @param -elevel \b IN : debug level
3171 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3172 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3173 {
3174 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3175
3176 switch (eLevel)
3177 {
3178 case E_VPU_EX_UART_LEVEL_ERR:
3179 {
3180 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3181 break;
3182 }
3183 case E_VPU_EX_UART_LEVEL_INFO:
3184 {
3185 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3186 break;
3187 }
3188 case E_VPU_EX_UART_LEVEL_DBG:
3189 {
3190 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3191 break;
3192 }
3193 case E_VPU_EX_UART_LEVEL_TRACE:
3194 {
3195 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3196 break;
3197 }
3198 case E_VPU_EX_UART_LEVEL_FW:
3199 {
3200 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3201 break;
3202 }
3203 default:
3204 {
3205 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3206 break;
3207 }
3208 }
3209 }
3210
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3211 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3212 {
3213 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3214 MS_U32 u32CmdArg = (MS_U32)eVerType;
3215 MS_U32 u32Version = 0xFFFFFFFF;
3216 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3217 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3218 {
3219 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3220 return u32Version;
3221 }
3222
3223 MS_BOOL bRet = false;
3224 MS_U32 u32TimeOut = 0xFFFFFFFF;
3225
3226 while(--u32TimeOut)
3227 {
3228 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3229 {
3230 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3231 if (false == bRet)
3232 {
3233 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3234 return u32Version;
3235 }
3236
3237 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3238 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3239 return u32Version;
3240 }
3241 }
3242
3243 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3244
3245 return u32Version;
3246 }
3247
HAL_VPU_EX_NotSupportDS(void)3248 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3249 {
3250 return FALSE;
3251 }
3252
3253 //-----------------------------------------------------------------------------
3254 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3255 /// @brief \b Function \b Description: Get VPU MIU base address
3256 /// @return - vpu MIU1 base
3257 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3258 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3259 {
3260 return VPU_MIU1BASE_ADDR;
3261 }
3262
3263
HAL_VPU_EX_GetSHMAddr(void)3264 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3265 {
3266 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3267 {
3268 return 0;
3269 }
3270 return pVPUHalContext->u32VPUSHMAddr;
3271 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3272 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3273 {
3274 pVPUHalContext->bEnableVPUSecureMode = enable;
3275 return TRUE;
3276 }
3277
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3278 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3279 {
3280 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3281
3282 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3283 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3284 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3285 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3286 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3287 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3288 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3289 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3290
3291 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3292 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3293 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3294 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3295 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3296 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3297 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3298 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3299 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3300 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3301
3302 return TRUE;
3303 }
3304
3305 //-----------------------------------------------------------------------------
3306 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3307 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3308 /// @return - success/fail
3309 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3310 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3311 {
3312 #define MAX_CAPABILITY_INFO_NUM 8
3313 #define MAX_CODEC_TYPE_NUM 18
3314
3315 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3316 {
3317 //width, height , frmrate, profile, level, version bit rate reserved2
3318 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3319 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3320 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3321 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3322 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3323 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3324 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3325 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3326 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3327 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3328 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3329 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3330 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3331 { 1280, 720, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3332 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_MVC
3333 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3334 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3335 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3336 };
3337
3338 if(eCodecType < MAX_CODEC_TYPE_NUM)
3339 {
3340 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3341 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3342 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3343 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3344 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3345 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3346 return TRUE;
3347 }
3348 else
3349 {
3350 return FALSE;
3351 }
3352 }
3353
3354 #ifdef VDEC3
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bIsNstreamMode)3355 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode)
3356 {
3357 MS_U32 i, max_bbu_cnt;
3358 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3359
3360 if(pTaskInfo == NULL)
3361 return retBBUId;
3362
3363 BBU_STATE *bbu_state;
3364 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3365 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3366
3367 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3368
3369 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3370
3371 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3372 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3373 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3374
3375 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3376 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3377
3378 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3379 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3380 */
3381 #if 1
3382 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3383 {
3384 if (bTSP)
3385 {
3386 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3387 {
3388 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3389 slq_state[u8TaskId].bTSP = TRUE;
3390 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3391 return u8TaskId;
3392 }
3393 }
3394 else
3395 {
3396 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3397 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3398 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3399 {
3400 if (slq_state[i].u32Used != 0)
3401 {
3402 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3403 {
3404 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3405 }
3406 }
3407 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3408 {
3409 avaliable_bbu_idx = i; // recored the first empty bbu
3410 }
3411 }
3412
3413 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // In Nstream mode, first priority is sharing bbu
3414 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3415 slq_state[shared_bbu_idx].bTSP = FALSE;
3416 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3417 return avaliable_bbu_idx;
3418 }
3419 else if (slq_state[u8TaskId].u32Used == FALSE) { // 2nd priority is task id
3420 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3421 slq_state[u8TaskId].bTSP = FALSE;
3422 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3423 return u8TaskId;
3424 }
3425 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3426 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3427 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3428 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3429 return avaliable_bbu_idx;
3430 }
3431 else {
3432 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3433 }
3434 }
3435 }
3436 #if SUPPORT_G2VP9
3437 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3438 {
3439 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3440 // Don't care the return value, G2_VP9 will not use it.
3441 return 0;
3442 }
3443 #endif
3444 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3445 {
3446 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3447 // Don't care the return value, VP8 will not use it.
3448 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3449 return u8Offset;
3450 //return 0;
3451 }
3452 else
3453 {
3454 switch (pTaskInfo->eDecType)
3455 {
3456 case E_VPU_EX_DECODER_EVD:
3457 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3458 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3459 break;
3460 case E_VPU_EX_DECODER_HVD:
3461 case E_VPU_EX_DECODER_RVD:
3462 case E_VPU_EX_DECODER_MVC:
3463 default:
3464 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3465 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3466 break;
3467 }
3468
3469 if (bTSP)
3470 {
3471 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3472 {
3473 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3474 bbu_state[u8TaskId].bTSP = TRUE;
3475 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3476 slq_state[u8TaskId].bTSP = TRUE;
3477 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3478 return u8TaskId;
3479 }
3480 }
3481 else
3482 {
3483 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3484 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3485 for (i = 0; i < max_bbu_cnt; i++)
3486 {
3487 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3488 {
3489 if (bbu_state[i].bTSP == FALSE)
3490 {
3491 shared_bbu_idx = i;
3492 }
3493 }
3494 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3495 {
3496 avaliable_bbu_idx = i;
3497 }
3498 }
3499 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // // In Nstream mode, first priority is sharing bbu
3500 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3501 return shared_bbu_idx;
3502 }
3503 else if (bbu_state[u8TaskId].u32Used == FALSE) { // 2nd priority is task id
3504 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3505 return u8TaskId;
3506 }
3507 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3508 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3509 return avaliable_bbu_idx;
3510 }
3511 else {
3512 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3513 }
3514 }
3515 }
3516 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3517 MS_U32 j;
3518 MS_BOOL Got = FALSE;
3519 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3520 {
3521 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3522 {
3523 if(slq_state[i].u32Used != 0)
3524 {
3525 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3526 {
3527 retBBUId = i;
3528 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3529 slq_state[retBBUId].bTSP = bTSP;
3530 slq_state[retBBUId].bUsedbyMVD = TRUE;
3531 return retBBUId;
3532 }
3533 }
3534 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3535 {
3536 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3537 {
3538 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3539 {
3540 Got = TRUE;
3541 retBBUId = i;
3542 }
3543 }
3544
3545 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3546 {
3547 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3548 {
3549 Got = TRUE;
3550 retBBUId = i;
3551 }
3552 }
3553
3554 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3555 retBBUId = i;
3556 }
3557 }
3558 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3559 {
3560 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3561 slq_state[retBBUId].bTSP = bTSP;
3562 slq_state[retBBUId].bUsedbyMVD = TRUE;
3563 }
3564 }
3565 #if SUPPORT_G2VP9
3566 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3567 {
3568 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3569 // Don't care the return value, G2_VP9 will not use it.
3570 return 0;
3571 }
3572 #endif
3573 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3574 {
3575 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3576 // Don't care the return value, VP8 will not use it.
3577 return 0;
3578 }
3579 else // HVD/EVD case
3580 {
3581 switch (pTaskInfo->eDecType)
3582 {
3583 case E_VPU_EX_DECODER_EVD:
3584 case E_VPU_EX_DECODER_G2VP9:
3585 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3586 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3587 break;
3588 case E_VPU_EX_DECODER_HVD:
3589 case E_VPU_EX_DECODER_RVD:
3590 case E_VPU_EX_DECODER_MVC:
3591 default:
3592 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3593 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3594 break;
3595 }
3596
3597 for (i = 0; i < max_bbu_cnt; i++)
3598 {
3599 if(bbu_state[i].u32Used != 0)
3600 {
3601 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3602 {
3603 retBBUId = i;
3604 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3605 bbu_state[retBBUId].bTSP = bTSP;
3606 return retBBUId;
3607 }
3608 }
3609 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3610 {
3611 if(i < MAX_MVD_SLQ_COUNT)
3612 {
3613 if(!bTSP) //HVD/EVD first MM case
3614 {
3615 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3616 {
3617 retBBUId = i;
3618 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3619 bbu_state[retBBUId].bTSP = bTSP;
3620 return retBBUId;
3621 }
3622
3623 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3624 retBBUId = i;
3625 }
3626 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3627 {
3628 retBBUId = i;
3629 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3630 bbu_state[retBBUId].bTSP = bTSP;
3631 slq_state[retBBUId].bUsedbyMVD = FALSE;
3632 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3633 slq_state[retBBUId].bTSP = bTSP;
3634 return retBBUId;
3635 }
3636 }
3637 }
3638 }
3639 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3640 {
3641 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3642 bbu_state[retBBUId].bTSP = bTSP;
3643 if(bTSP)
3644 {
3645 slq_state[retBBUId].bUsedbyMVD = FALSE;
3646 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3647 slq_state[retBBUId].bTSP = bTSP;
3648 }
3649 }
3650 }
3651 #endif
3652 return retBBUId;
3653 }
3654
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3655 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3656 {
3657 MS_U32 max_bbu_cnt;
3658 BBU_STATE *bbu_state;
3659 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3660
3661 if(pTaskInfo == NULL)
3662 return FALSE;
3663 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3664 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3665
3666 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3667 /* MS_U32 i;
3668 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3669 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3670
3671 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3672 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3673
3674 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3675 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3676 */
3677 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3678 {
3679 // TO DO
3680 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3681 {
3682 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3683 slq_state[u32BBUId].bTSP = FALSE;
3684 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3685 return TRUE;
3686 }
3687 }
3688 #if SUPPORT_G2VP9
3689 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3690 {
3691 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3692 return TRUE;
3693 }
3694 #endif
3695 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3696 {
3697 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3698 return TRUE;
3699 }
3700 else
3701 {
3702 switch (pTaskInfo->eDecType)
3703 {
3704 case E_VPU_EX_DECODER_EVD:
3705 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3706 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3707 break;
3708 case E_VPU_EX_DECODER_HVD:
3709 case E_VPU_EX_DECODER_RVD:
3710 case E_VPU_EX_DECODER_MVC:
3711 default:
3712 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3713 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3714 break;
3715 }
3716
3717 if (u32BBUId < max_bbu_cnt)
3718 {
3719 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
3720 bbu_state[u32BBUId].bTSP = FALSE;
3721 if (bTSP)
3722 {
3723 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3724 slq_state[u32BBUId].bTSP = FALSE;
3725 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3726 }
3727 return TRUE;
3728 }
3729 }
3730 return FALSE;
3731 }
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)3732 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
3733 {
3734 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3735
3736 if (CHECK_NULL_PTR(pstVBBU))
3737 return 0;
3738 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3739 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
3740 MS_U32 u32Vacancy = 0;
3741
3742 if (u32WrPtr == u32RdPtr)
3743 {
3744 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
3745 }
3746 else if (u32WrPtr > u32RdPtr)
3747 {
3748 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
3749 }
3750 else
3751 {
3752 u32Vacancy = u32RdPtr - u32WrPtr - 1;
3753 }
3754
3755 return u32Vacancy;
3756 }
3757
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)3758 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
3759 {
3760 return MAX_VDEC_VBBU_ENTRY_COUNT;
3761 }
3762
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3763 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3764 {
3765 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3766 #if SUPPORT_G2VP9
3767 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3768 #endif
3769
3770 if (CHECK_NULL_PTR(pstVBBU))
3771 return FALSE;
3772 MsOS_ReadMemory();
3773 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
3774
3775 if(NULL == stEntry)
3776 {
3777 return 0;
3778 }
3779
3780 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
3781 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
3782 {
3783 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
3784 }
3785 else
3786 {
3787 #if SUPPORT_G2VP9
3788 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3789 {
3790 if (stEntry->u32Offset == 0)
3791 return 0;
3792 else
3793 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3794 }
3795 else
3796 #endif
3797 {
3798 return stEntry->u32Offset;
3799 }
3800 }
3801 }
3802
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3803 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3804 {
3805 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3806 VDEC_VBBU_Entry *stEntry;
3807 #if SUPPORT_G2VP9
3808 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3809 #endif
3810
3811 MsOS_ReadMemory();
3812 if (CHECK_NULL_PTR(pstVBBU))
3813 return 0;
3814 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3815
3816 if (u32WrPtr == 0)
3817 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
3818 else
3819 u32WrPtr--;
3820
3821 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
3822
3823 if(NULL == stEntry)
3824 {
3825 return 0;
3826 }
3827
3828 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
3829 #if SUPPORT_G2VP9
3830 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3831 {
3832 if (stEntry->u32Offset == 0)
3833 return 0;
3834 else
3835 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3836 }
3837 else
3838 #endif
3839 {
3840 return stEntry->u32Offset + stEntry->u32Length;
3841 }
3842 }
3843
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)3844 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
3845 {
3846 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3847 #if SUPPORT_G2VP9
3848 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3849 #endif
3850
3851 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
3852 return FALSE;
3853 MsOS_ReadMemory();
3854 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
3855 MS_U32 u32NewWrPtr;
3856
3857 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
3858 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
3859 {
3860 u32NewWrPtr = 0;
3861 }
3862
3863 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
3864
3865 stEntry->u32Offset = stVpuPkt->u32Offset;
3866
3867 #if SUPPORT_G2VP9
3868 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3869 {
3870 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3871 }
3872 #endif
3873
3874 stEntry->u32Length = stVpuPkt->u32Length;
3875 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
3876 stEntry->u32ID_H = stVpuPkt->u32ID_H;
3877 stEntry->u32ID_L = stVpuPkt->u32ID_L;
3878
3879 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
3880
3881 pstVBBU->u32WrPtr = u32NewWrPtr;
3882
3883 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
3884
3885 MsOS_FlushMemory();
3886
3887 return TRUE;
3888 }
3889
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)3890 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
3891 {
3892 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3893
3894 if (CHECK_NULL_PTR(pstVBBU))
3895 return FALSE;
3896 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
3897 }
3898
3899 ///-----------------------------------------------------------------------------
3900 /// specify the command send to Mail box or DRAM
3901 /// @return TRUE or FALSE
3902 /// - TRUE, Mail box
3903 /// - FALSE, Dram
3904 /// @param u32Cmd \b IN: Command is going to be sned
3905 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)3906 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
3907 {
3908 MS_BOOL bResult = TRUE;
3909
3910 switch (u32Cmd)
3911 {
3912 // *********** Runtime action Command
3913 /* case E_HVD_CMD_RELEASE_DISPQ:
3914 case E_HVD_CMD_UPDATE_DISPQ:
3915 case E_HVD_CMD_FLUSH_DEC_Q:
3916 case E_HVD_CMD_FLUSH:
3917 case E_HVD_CMD_PLAY:
3918 case E_HVD_CMD_PAUSE:
3919 case E_HVD_CMD_STOP:
3920 case E_HVD_CMD_STEP_DECODE:
3921 case E_HVD_CMD_SKIP_DEC:
3922 case E_HVD_CMD_DISP_I_DIRECT:*/
3923 // *********** Dual-Stream Create Task Command
3924 case E_DUAL_CMD_TASK0_HVD_BBU:
3925 case E_DUAL_CMD_TASK0_HVD_TSP:
3926 case E_DUAL_CMD_TASK0_MVD_SLQ:
3927 case E_DUAL_CMD_TASK0_MVD_TSP:
3928 case E_DUAL_CMD_TASK1_HVD_BBU:
3929 case E_DUAL_CMD_TASK1_HVD_TSP:
3930 case E_DUAL_CMD_MODE:
3931 #ifndef _WIN32
3932 case E_DUAL_CMD_TASK1_MVD_SLQ:
3933 case E_DUAL_CMD_TASK1_MVD_TSP:
3934 #endif
3935 case E_DUAL_CMD_DEL_TASK:
3936 case E_DUAL_CMD_SINGLE_TASK:
3937 case E_DUAL_VERSION:
3938 case E_DUAL_R2_CMD_EXIT:
3939 #ifdef VDEC3
3940 case E_DUAL_R2_CMD_FBADDR:
3941 case E_DUAL_R2_CMD_FBSIZE:
3942 // *********** N-Streams
3943 case E_NST_CMD_TASK_HVD_TSP:
3944 case E_NST_CMD_TASK_HVD_BBU:
3945 case E_NST_CMD_TASK_MVD_TSP:
3946 case E_NST_CMD_TASK_MVD_SLQ:
3947 case E_NST_CMD_DEL_TASK:
3948 #endif
3949 case E_DUAL_CMD_COMMON:
3950 {
3951 bResult = TRUE;
3952 }
3953 break;
3954 default:
3955 {
3956 bResult = FALSE;
3957 }
3958 break;
3959 }
3960
3961 return bResult;
3962 }
3963
3964 ///-----------------------------------------------------------------------------
3965 /// specify the command send to Mail box or DRAM
3966 /// @return TRUE or FALSE
3967 /// - TRUE, Mail box
3968 /// - FALSE, Dram
3969 /// @param u32Cmd \b IN: Command is going to be sned
3970 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)3971 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
3972 {
3973 MS_BOOL bResult = TRUE;
3974
3975 switch (u32Cmd)
3976 {
3977 // *********** Runtime action Command
3978 case E_HVD_CMD_RELEASE_DISPQ:
3979 case E_HVD_CMD_UPDATE_DISPQ:
3980 case E_HVD_CMD_FLUSH_DEC_Q:
3981 case E_HVD_CMD_PAUSE:
3982 case E_HVD_CMD_FLUSH:
3983 case E_HVD_CMD_PLAY:
3984 case E_HVD_CMD_STOP:
3985 case E_HVD_CMD_SKIP_DEC:
3986 case E_HVD_CMD_DISP_I_DIRECT:
3987 case E_HVD_CMD_STEP_DECODE:
3988 case E_HVD_CMD_INC_DISPQ_NUM:
3989 {
3990 bResult = TRUE;
3991 }
3992 break;
3993 default:
3994 {
3995 bResult = FALSE;
3996 }
3997 break;
3998 }
3999
4000 return bResult;
4001 }
4002
4003 ///-----------------------------------------------------------------------------
4004 /// Send message to HVD stream command queue
4005 /// @return TRUE or FALSE
4006 /// - TRUE, Success
4007 /// - FALSE, Failed
4008 /// @param u32DramAddr \b IN: address to be writen
4009 /// @param u32Msg \b IN: data to be writen
4010 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4011 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4012 {
4013 MS_BOOL bResult = TRUE;
4014
4015 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4016
4017 WRITE_LONG(u32DramAddr,u32Msg);
4018
4019 return bResult;
4020 }
4021
4022 ///-----------------------------------------------------------------------------
4023 /// Read task share memory to specify that task command queue is empty or not
4024 /// @return TRUE or FALSE
4025 /// - TRUE, Empty
4026 /// - FALSE, Non empty
4027 /// @param u32Id \b IN: Task information
4028 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4029 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4030 {
4031 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4032 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4033 if (!cmd_q)
4034 {
4035 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4036 return FALSE;
4037 }
4038
4039 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4040 }
4041
4042 ///-----------------------------------------------------------------------------
4043 /// Read task share memory to specify that task command queue is full or not
4044 /// @return TRUE or FALSE
4045 /// - TRUE, Full
4046 /// - FALSE, Non full
4047 /// @param u32Id \b IN: Task information
4048 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4049 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4050 {
4051 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4052 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4053 if (!cmd_q)
4054 {
4055 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4056 return TRUE;
4057 }
4058 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4059
4060 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4061 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4062
4063 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4064 }
4065
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4066 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4067 {
4068 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4069 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4070 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4071
4072 #if HVD_ENABLE_MVC
4073 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4074 {
4075 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4076 }
4077 #endif
4078
4079 if (CHECK_NULL_PTR(cmd_q))
4080 {
4081 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4082 return bResult;
4083 }
4084 MS_VIRT u32CmdQWdPtr;
4085
4086 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4087 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4088
4089 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4090 return E_HVD_COMMAND_QUEUE_FULL;
4091 else
4092 {
4093 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4094 }
4095
4096 switch (u8CmdType)
4097 {
4098 case E_HVD_CMDQ_CMD:
4099 {
4100 u32Msg |= (u8TaskID << VDEC_BBU_ID_SHIFT);
4101 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4102
4103 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4104
4105 if (bResult)
4106 {
4107 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4108
4109 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4110 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4111
4112 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4113 }
4114 break;
4115 }
4116 case E_HVD_CMDQ_ARG:
4117 {
4118 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4119 if (bResult)
4120 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4121 break;
4122 }
4123 default:
4124 {
4125 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4126 break;
4127 }
4128 }
4129
4130 MsOS_FlushMemory();
4131
4132 return bResult;
4133 }
4134
4135 ///-----------------------------------------------------------------------------
4136 /// Read task share memory to specify that task display command queue is empty or not
4137 /// @return TRUE or FALSE
4138 /// - TRUE, Empty
4139 /// - FALSE, Non empty
4140 /// @param u32Id \b IN: Task information
4141 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4142 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4143 {
4144 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4145 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4146 if (!cmd_q)
4147 {
4148 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4149 return FALSE;
4150 }
4151
4152 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4153 }
4154
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4155 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4156 {
4157 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4158 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4159 if (!cmd_q)
4160 {
4161 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4162 return TRUE;
4163 }
4164
4165 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4166
4167 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4168 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4169
4170 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4171 }
4172
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4173 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4174 {
4175 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4176 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4177 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4178
4179 #if HVD_ENABLE_MVC
4180 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4181 {
4182 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4183 }
4184 #endif
4185
4186 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4187 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4188
4189 if (CHECK_NULL_PTR(cmd_q))
4190 {
4191 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4192 return bResult;
4193 }
4194
4195 MS_VIRT u32DISPCMDQWdPtr;
4196
4197 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4198 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4199
4200 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4201 return E_HVD_COMMAND_QUEUE_FULL;
4202 else
4203 {
4204 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4205 }
4206
4207 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4208
4209 switch (u8CmdType)
4210 {
4211 case E_HVD_CMDQ_CMD:
4212 {
4213 u32Msg |= (u8TaskID << VDEC_BBU_ID_SHIFT);
4214 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4215
4216 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4217
4218 if (bResult)
4219 {
4220 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4221
4222 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4223 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4224
4225 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4226 }
4227 break;
4228 }
4229 case E_HVD_CMDQ_ARG:
4230 {
4231 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4232 if (bResult)
4233 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4234 break;
4235 }
4236 default:
4237 {
4238 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4239 break;
4240 }
4241 }
4242
4243 MsOS_FlushMemory();
4244
4245 return bResult;
4246 }
4247
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4248 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4249 {
4250 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4251 MS_U32 u32StAddr;
4252 MS_U8 u8TmpMiuSel;
4253
4254 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4255
4256 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4257
4258 return TRUE;
4259 }
4260 #endif
4261
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4262 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4263 {
4264 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4265
4266 if(u32address >= HAL_MIU1_BASE)
4267 {
4268 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4269 }
4270 else
4271 {
4272 pVPUHalContext->u32DynamicFBAddress = u32address;
4273 }
4274
4275 pVPUHalContext->u32DynamicFBSize = u32Size;
4276 }
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4277 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4278 {
4279 MS_SIZE FrameBufferSize = 0;
4280
4281 switch(eCodecType)
4282 {
4283 case E_VPU_EX_CODEC_TYPE_MPEG2:
4284 case E_VPU_EX_CODEC_TYPE_H263:
4285 case E_VPU_EX_CODEC_TYPE_MPEG4:
4286 case E_VPU_EX_CODEC_TYPE_DIVX311:
4287 case E_VPU_EX_CODEC_TYPE_DIVX412:
4288 case E_VPU_EX_CODEC_TYPE_FLV:
4289 FrameBufferSize = 0x1E00000;
4290 break;
4291 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4292 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4293 FrameBufferSize = 0x6C00000;
4294 break;
4295 case E_VPU_EX_CODEC_TYPE_RV8:
4296 case E_VPU_EX_CODEC_TYPE_RV9:
4297 FrameBufferSize = 0x1B00000;
4298 break;
4299 case E_VPU_EX_CODEC_TYPE_VP8:
4300 FrameBufferSize = 0x1500000;
4301 break;
4302 case E_VPU_EX_CODEC_TYPE_H264:
4303 FrameBufferSize = 0x8200000;
4304 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4305 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4306 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4307 break;
4308 case E_VPU_EX_CODEC_TYPE_AVS:
4309 FrameBufferSize = 0x1B00000;
4310 break;
4311 case E_VPU_EX_CODEC_TYPE_MJPEG:
4312 FrameBufferSize = 0x2800000;
4313 break;
4314 case E_VPU_EX_CODEC_TYPE_MVC:
4315 FrameBufferSize = 0x4200000;
4316 break;
4317 case E_VPU_EX_CODEC_TYPE_HEVC:
4318 #if SUPPORT_MSVP9
4319 case E_VPU_EX_CODEC_TYPE_VP9:
4320 #endif
4321 FrameBufferSize = 0xA000000;
4322 break;
4323 #if !SUPPORT_MSVP9
4324 case E_VPU_EX_CODEC_TYPE_VP9:
4325 FrameBufferSize = 0x7800000;
4326 break;
4327 #endif
4328 default:
4329 FrameBufferSize = 0;
4330 break;
4331 }
4332
4333 return FrameBufferSize;
4334 }
4335
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4336 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4337 {
4338 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4339 }
4340
4341 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4342 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4343 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4344 {
4345 MS_SIZE FrameBufferSize = 0;
4346
4347 if (!offset || !length)
4348 return FALSE;
4349
4350 total_length -= unUseSize;
4351 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4352 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4353
4354 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4355
4356 if(FrameBufferSize == 0)
4357 {
4358 return FALSE;
4359 }
4360 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4361 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4362 if (total_length < FrameBufferSize)
4363 {
4364 *offset = unUseSize;
4365 *length = total_length;
4366 }
4367 else // todo, dual decode case
4368 {
4369 *offset = unUseSize;
4370 *length = FrameBufferSize;
4371 }
4372 return TRUE;
4373 }
4374
HAL_VPU_EX_strcmp(const char * string1,const char * string2)4375 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
4376 {
4377 int iRet, i;
4378
4379 i = 0;
4380 while(string1[i] || string2[i])
4381 {
4382 iRet = string1[i] - string2[i];
4383 if(iRet)
4384 {
4385 return iRet;
4386 }
4387 i++;
4388 }
4389 return 0;
4390 }
4391
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)4392 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
4393 {
4394 typedef enum
4395 {
4396 E_CAP_NDEC_FB_MIU_SELECT,
4397 E_CAP_NDEC_NSTREAM_FB_SIZE,
4398 E_CAP_NDEC_NSTREAM_BS_SIZE,
4399 E_CAP_NDEC_SUPPORT_SHAREBBU,
4400 E_CAP_SUPPORT_ALLOCATOR,
4401
4402 } VPU_EX_GetCapabilityCmdId;
4403
4404 typedef struct
4405 {
4406 VPU_EX_GetCapabilityCmdId eCmdId;
4407 MS_U8 u8CmdName[32];
4408
4409 } VPU_EX_GetCapabilityCmd;
4410
4411 static VPU_EX_GetCapabilityCmd stCapCmd[] =
4412 {
4413 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
4414 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
4415 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
4416 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
4417 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
4418 };
4419
4420 MS_U32 bRet = FALSE;
4421 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
4422 MS_U32 u32CmdCnt;
4423
4424 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
4425 {
4426 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
4427 {
4428 bRet = TRUE;
4429 switch(stCapCmd[u32CmdCnt].eCmdId)
4430 {
4431 case E_CAP_NDEC_FB_MIU_SELECT:
4432 {
4433 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4434 *pSupport = FALSE;
4435 }
4436 break;
4437
4438 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
4439 case E_CAP_NDEC_NSTREAM_FB_SIZE:
4440 {
4441 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4442 *pSize = 0;
4443 }
4444 break;
4445
4446 // FIXME: Patch for waiting dynamic bitstream buffer
4447 case E_CAP_NDEC_NSTREAM_BS_SIZE:
4448 {
4449 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4450 *pSize = 0;
4451 }
4452 break;
4453
4454 case E_CAP_NDEC_SUPPORT_SHAREBBU:
4455 {
4456 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
4457 *pbSupportShareBBU = FALSE;
4458 }
4459 break;
4460
4461 case E_CAP_SUPPORT_ALLOCATOR:
4462 {
4463 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4464 *pSupport = FALSE;
4465 }
4466 break;
4467
4468 default:
4469 bRet = FALSE;
4470 break;
4471 }
4472 }
4473 }
4474
4475 return bRet;
4476 }
4477
4478 #else
4479 #include "halVPU_EX.h"
4480 #include "drvMMIO.h"
4481 #include "../../../../vdec_v2/hal/manhattan/hvd_ex/regHVD_EX.h"
4482 #include "halCHIP.h"
4483
4484 #if defined(MSOS_TYPE_NUTTX)
4485 extern int lib_lowprintf(const char *fmt, ...);
4486 #define PRINTF lib_lowprintf
4487 #elif defined(MSOS_TYPE_OPTEE)
4488 #define PRINTF printf
4489 #endif
4490
4491 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
4492 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
4493
4494 MS_U8 u8FW_Binary[] = {
4495 #include "fwVPU.dat"
4496 };
4497
4498 MS_U32 u32HVDRegOSBase;
4499
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)4500 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
4501 {
4502 //PRINTF("do load code,u32DestAddr %x\n",addr);
4503 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
4504 MAsm_CPU_Sync();
4505 MsOS_FlushMemory();
4506
4507 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
4508 {
4509 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
4510 return FALSE;
4511 }
4512 return TRUE;
4513 }
4514
HAL_VPU_EX_SetLockDownRegister(void * param)4515 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
4516 {
4517 #if 1
4518 MS_PHY u32StAddr_main;
4519 MS_PHY u32StAddr_sub;
4520 MS_U32 u32NonPMBankSize = 0;
4521 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
4522
4523 if(param == NULL)
4524 {
4525 return FALSE;
4526 }
4527
4528 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
4529
4530 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
4531
4532 // ES buffer
4533 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
4534 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
4535
4536
4537 MS_PHY u32StartOffset;
4538 MS_U8 u8MiuSel;
4539
4540 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
4541 u32StAddr_main = u32StartOffset;
4542
4543 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
4544 u32StAddr_sub = u32StartOffset;
4545
4546 //Lock down register
4547 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
4548 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
4549
4550 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
4551 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
4552 //~
4553
4554 // Lock Down
4555 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
4556 //~
4557 #endif
4558 return TRUE;
4559 }
4560
4561 #endif
4562