1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216 typedef struct
217 {
218 MS_BOOL bSTCSetMode;
219 MS_U32 u32STCIndex;
220 } VPU_EX_STC;
221
222 #include "ULog.h"
223 #define VPU_MSG_ERR(format, args...) \
224 do \
225 { \
226 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
227 { \
228 ULOGE("VPU", "[ERR]%s:", __FUNCTION__); \
229 ULOGE("VPU", format, ##args); \
230 } \
231 } while (0)
232
233 #define VPU_MSG_DBG(format, args...) \
234 do \
235 { \
236 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
237 { \
238 ULOGD("VPU", "[DBG]%s:", __FUNCTION__); \
239 ULOGD("VPU", format, ##args); \
240 } \
241 } while (0)
242
243 #define VPU_MSG_INFO(format, args...) \
244 do \
245 { \
246 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
247 { \
248 ULOGI("VPU", "[INF]%s:", __FUNCTION__); \
249 ULOGI("VPU", format, ##args); \
250 } \
251 } while (0)
252
253 //------------------------------ MIU SETTINGS ----------------------------------
254 #ifdef EVDR2
255 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
256 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
257 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))
258
259 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
260 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
261 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
262
263 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
264 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
265 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
266
267
268 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
269 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
270 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
271 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
272 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
273 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
274 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
275 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
276 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))) //g08
277 #endif
278
279
280
281 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
282 do \
283 { \
284 if (miu_clients##_ON_MIU0 == 1) \
285 { \
286 _MaskMiuReq_##miu_clients(mask); \
287 } \
288 else \
289 { \
290 if (miu_clients##_ON_MIU1 == 1) \
291 { \
292 _MaskMiu1Req_##miu_clients(mask); \
293 } \
294 else if (miu_clients##_ON_MIU2 == 1) \
295 { \
296 _MaskMiu2Req_##miu_clients(mask); \
297 } \
298 } \
299 } while(0)
300
301
302
303
304 #if ENABLE_VPU_MUTEX_PROTECTION
305 MS_S32 s32VPUMutexID = -1;
306 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
307
308 #define _HAL_VPU_MutexCreate() \
309 if (s32VPUMutexID < 0) \
310 { \
311 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
312 }
313
314 #define _HAL_VPU_MutexDelete() \
315 if (s32VPUMutexID >= 0) \
316 { \
317 MsOS_DeleteMutex(s32VPUMutexID); \
318 s32VPUMutexID = -1; \
319 }
320
321 #define _HAL_VPU_Entry() \
322 if (s32VPUMutexID >= 0) \
323 { \
324 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
325 { \
326 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
327 } \
328 }
329
330 #define _HAL_VPU_Return(_ret) \
331 { \
332 if (s32VPUMutexID >= 0) \
333 { \
334 MsOS_ReleaseMutex(s32VPUMutexID); \
335 } \
336 return _ret; \
337 }
338
339 #define _HAL_VPU_Release() \
340 { \
341 if (s32VPUMutexID >= 0) \
342 { \
343 MsOS_ReleaseMutex(s32VPUMutexID); \
344 } \
345 }
346 #else
347 #define _HAL_VPU_MutexCreate()
348 #define _HAL_VPU_MutexDelete()
349 #define _HAL_VPU_Entry()
350 #define _HAL_VPU_Return(_ret) {return _ret;}
351 #define _HAL_VPU_Release()
352 #endif
353
354 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
355 #define VPU_CMD_TIMEOUT 1000 // 1 sec
356
357
358 #if( !defined(MSOS_TYPE_LINUX_KERNEL) && !defined(ANDROID))
359 #define VPU_FIELD_DETECTOR TRUE
360 #else
361 #define VPU_FIELD_DETECTOR FALSE
362 #endif
363
364 //-------------------------------------------------------------------------------------------------
365 // Local Structures
366 //-------------------------------------------------------------------------------------------------
367 typedef struct _VPU_HWInitFunc
368 {
369 MS_BOOL (*pfMVDHW_Init)(void);
370 MS_BOOL (*pfMVDHW_Deinit)(void);
371 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
372 MS_BOOL (*pfHVDHW_Deinit)(void);
373 } VPU_HWInitFunc;
374
375 typedef struct
376 {
377 MS_U32 u32ApiHW_Version; //<Version of current structure>
378 MS_U16 u16ApiHW_Length; //<Length of this structure>
379
380 MS_U8 u8Cap_Support_Decoder_Num;
381
382 MS_BOOL bCap_Support_MPEG2;
383 MS_BOOL bCap_Support_H263;
384 MS_BOOL bCap_Support_MPEG4;
385 MS_BOOL bCap_Support_DIVX311;
386 MS_BOOL bCap_Support_DIVX412;
387 MS_BOOL bCap_Support_FLV;
388 MS_BOOL bCap_Support_VC1ADV;
389 MS_BOOL bCap_Support_VC1MAIN;
390
391 MS_BOOL bCap_Support_RV8;
392 MS_BOOL bCap_Support_RV9;
393 MS_BOOL bCap_Support_H264;
394 MS_BOOL bCap_Support_AVS;
395 MS_BOOL bCap_Support_AVS_PLUS;
396 MS_BOOL bCap_Support_MJPEG;
397 MS_BOOL bCap_Support_MVC;
398 MS_BOOL bCap_Support_VP8;
399 MS_BOOL bCap_Support_VP9;
400 MS_BOOL bCap_Support_HEVC;
401
402 /*New HW Cap and Feature add in struct at the end*/
403 }VDEC_HwCap;
404
405 //-------------------------------------------------------------------------------------------------
406 // Local Functions Prototype
407 //-------------------------------------------------------------------------------------------------
408 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
409 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
410 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
411
412 //-------------------------------------------------------------------------------------------------
413 // Global Variables
414 //-------------------------------------------------------------------------------------------------
415 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
416 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
417 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
418 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
419 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
420 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
421 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
422 #if SUPPORT_G2VP9 && defined(VDEC3)
423 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
424 #endif
425 #if defined (__aeon__)
426 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
427 #else
428 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
429 #endif
430
431 //-------------------------------------------------------------------------------------------------
432 // Local Variables
433 //-------------------------------------------------------------------------------------------------
434 #if 0
435
436 static MS_BOOL _bVPUPowered = FALSE;
437 static MS_BOOL _bVPURsted = FALSE;
438 static MS_BOOL _bVPUSingleMode = FALSE;
439 static VPU_EX_DecModCfg _stVPUDecMode;
440
441 static MS_U8 u8TaskCnt = 0;
442
443 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
444
445 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
446 static VPU_EX_Stream _stVPUStream[] =
447 {
448 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
449 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
450 };
451 static VPU_HWInitFunc stHWInitFunc =
452 {
453 &HAL_MVD_InitHW,
454 &HAL_MVD_DeinitHW,
455 &HAL_HVD_EX_InitHW,
456 &HAL_HVD_EX_DeinitHW,
457 };
458
459 #endif
460
461 #if VPU_ENABLE_EMBEDDED_FW_BINARY
462 static const MS_U8 u8HVD_FW_Binary[] = {
463 #include "fwVPU.dat"
464 };
465
466 #if HVD_ENABLE_RV_FEATURE
467 static const MS_U8 u8HVD_VLC_Binary[] = {
468 #include "fwVPU_VLC.dat"
469 };
470 #endif
471 #endif
472
473
474 #ifdef VDEC3
475 typedef struct
476 {
477 MS_BOOL bTSP;
478 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
479 MS_U32 u32Used;
480 } BBU_STATE;
481
482 typedef struct
483 {
484 MS_BOOL bTSP;
485 MS_BOOL bUsedbyMVD;
486 MS_U32 u32Used;
487 } SLQ_STATE;
488 #endif
489
490 typedef struct
491 {
492 MS_BOOL _bVPUPowered;
493 MS_BOOL _bVPURsted;
494 MS_BOOL _bVPUSingleMode;
495 VPU_EX_DecModCfg _stVPUDecMode;
496 MS_U8 u8TaskCnt;
497 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
498 #ifdef VDEC3
499 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
500 #else
501 VPU_EX_Stream _stVPUStream[2];
502 #endif
503
504 VPU_HWInitFunc stHWInitFunc;
505
506 MS_BOOL bVpuExReloadFW;
507 MS_BOOL bVpuExLoadFWRlt;
508 MS_VIRT u32VPUSHMAddr; //PA
509 MS_BOOL bEnableVPUSecureMode;
510
511 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
512 MS_BOOL bEnableDymanicFBMode;
513 MS_PHY u32DynamicFBAddress;
514 MS_U32 u32DynamicFBSize;
515 #ifdef VDEC3
516 MS_VIRT u32FWCodeAddr;
517 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
518
519 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
520 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
521 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
522
523 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
524 #endif
525 MS_U8 u8ForceRst;
526 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
527
528 MS_S32 s32VpuFdTaskId[MAX_SUPPORT_DECODER_NUM];
529 MS_BOOL bFDInit[MAX_SUPPORT_DECODER_NUM];
530
531 } VPU_Hal_CTX;
532
533 //global variables
534 VPU_Hal_CTX* pVPUHalContext = NULL;
535 VPU_Hal_CTX gVPUHalContext;
536 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
537 MS_BOOL bVPUMbxInitFlag = 0;
538 MS_U8 u8VPUMbxMsgClass = 0;
539 MBX_Msg VPUReeToTeeMbxMsg;
540 MBX_Msg VPUTeeToReeMbxMsg;
541
542 //-------------------------------------------------------------------------------------------------
543 // Debug Functions
544 //-------------------------------------------------------------------------------------------------
545
546
547 //-------------------------------------------------------------------------------------------------
548 // Local Functions
549 //-------------------------------------------------------------------------------------------------
550
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)551 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
552 {
553 #if HVD_ENABLE_RV_FEATURE
554 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
555 {
556 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
557 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
558 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
559
560 if (pVlcCfg->u32BinSize)
561 {
562 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
563
564 MS_U32 u32Start;
565 MS_U32 u32StartOffset;
566 MS_U8 u8MiuSel;
567
568 // Get MIU selection and offset from physical address = 0x30000000
569 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
570
571
572 if(u8MiuSel == E_CHIP_MIU_0)
573 cpyflag = E_SPIDMA_DEV_MIU0;
574 else if(u8MiuSel == E_CHIP_MIU_1)
575 cpyflag = E_SPIDMA_DEV_MIU1;
576 else if(u8MiuSel == E_CHIP_MIU_2)
577 cpyflag = E_SPIDMA_DEV_MIU2;
578
579 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
580 {
581 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
582 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
583
584 return FALSE;
585 }
586 }
587 else
588 {
589 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
590 return FALSE;
591 }
592 #else
593 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
594 return FALSE;
595 #endif
596 }
597 else
598 {
599 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
600 {
601 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
602 {
603 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
604 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
605
606 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
607 BDMA_Result bdmaRlt;
608 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
609
610 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
611 u32SrcAdd = pVlcCfg->u32BinAddr;
612 u32tabsize = pVlcCfg->u32BinSize;
613 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
614 MsOS_FlushMemory();
615 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
616
617 if (E_BDMA_OK != bdmaRlt)
618 {
619 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
620 }
621 #else
622 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
623 #endif
624 }
625 else
626 {
627 VPU_MSG_ERR
628 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
629 return FALSE;
630 }
631 }
632 else
633 {
634 #if VPU_ENABLE_EMBEDDED_FW_BINARY
635 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
636 MS_U8 *pu8HVD_VLC_Binary;
637
638 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
639
640 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
641 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
642 (MS_U32) sizeof(u8HVD_VLC_Binary));
643
644 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
645 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
646 #else
647 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
648 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
649 (MS_U32) sizeof(u8HVD_VLC_Binary));
650
651 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
652 #endif
653 #else
654 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
655 return FALSE;
656 #endif
657 }
658 }
659 #endif
660
661 return TRUE;
662 }
663
664 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)665 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
666 {
667 MS_U8 u8OffsetIdx = 0;
668 MS_U8 u8VSidBaseMask = 0xF0;
669 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
670
671 switch (eVSidBase)
672 {
673 case E_HAL_VPU_MAIN_STREAM_BASE:
674 {
675 u8OffsetIdx = 0;
676 break;
677 }
678 case E_HAL_VPU_SUB_STREAM_BASE:
679 {
680 u8OffsetIdx = 1;
681 break;
682 }
683 case E_HAL_VPU_MVC_STREAM_BASE:
684 {
685 u8OffsetIdx = 0;
686 break;
687 }
688 #ifdef VDEC3
689 case E_HAL_VPU_N_STREAM_BASE:
690 {
691 u8OffsetIdx = u32Id & 0x0F;
692 break;
693 }
694 #endif
695 default:
696 {
697 u8OffsetIdx = 0;
698 break;
699 }
700 }
701
702 /*
703 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
704 u32Id, eVSidBase, u8OffsetIdx);
705 */
706 return u8OffsetIdx;
707 }
708
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)709 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
710 {
711 return _VPU_EX_GetOffsetIdx(u32Id);
712 }
713
_VPU_EX_Context_Init(void)714 static void _VPU_EX_Context_Init(void)
715 {
716 #ifdef VDEC3
717 MS_U8 i;
718
719 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
720 {
721 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
722 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
723 }
724
725 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
726 {
727 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
728 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
729 }
730
731 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
732 {
733 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
734 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
735 }
736
737 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
738 {
739 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
740 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
741 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
742 }
743 #else
744 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
745 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
746 #endif
747 pVPUHalContext->bVpuExReloadFW = TRUE;
748 pVPUHalContext->u8ForceRst = 0;
749
750 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
751 {
752 pVPUHalContext->s32VpuFdTaskId[i] = -1;
753 pVPUHalContext->bFDInit[i] = FALSE;
754 }
755
756 }
757
HAL_VPU_EX_ForceSwRst(void)758 void HAL_VPU_EX_ForceSwRst(void)
759 {
760 pVPUHalContext->u8ForceRst = 1;
761 }
762
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)763 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
764 {
765 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
766 MS_U8 u8OffsetIdx = 0;
767
768 if (NULL == pTaskInfo)
769 {
770 return eCmd;
771 }
772
773 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
774
775 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
776 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
777
778 #ifdef VDEC3
779 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
780 {
781 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
782 {
783 eCmd = E_NST_CMD_TASK_MVD_TSP;
784 }
785 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
786 {
787 eCmd = E_NST_CMD_TASK_MVD_SLQ;
788 }
789 }
790 #else
791 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
792 {
793 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
794 {
795 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
796 }
797 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
798 {
799 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
800 }
801 }
802 #endif
803 #ifdef VDEC3
804 #if SUPPORT_G2VP9
805 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
806 #else
807 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
808 #endif
809 {
810 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
811 {
812 eCmd = E_NST_CMD_TASK_HVD_TSP;
813 }
814 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
815 {
816 eCmd = E_NST_CMD_TASK_HVD_BBU;
817 }
818 }
819 #else
820 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
821 {
822 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
823 {
824 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
825 }
826 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
827 {
828 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
829 }
830 }
831 #endif
832
833 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
834 return eCmd;
835 }
836
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)837 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
838 {
839 if (!pTaskInfo)
840 {
841 VPU_MSG_ERR("null input\n");
842 return FALSE;
843 }
844
845 //Check if we need to init MVD HW
846 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
847 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
848 {
849 //Init HW
850 if (FALSE == HAL_VPU_EX_MVDInUsed())
851 {
852 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
853 {
854 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
855 return FALSE;
856 }
857 }
858 else
859 {
860 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
861 }
862 }
863
864 //MVD use sub mvop
865 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
866 #ifdef VDEC3
867 (pTaskInfo->u8HalId == 1) )
868 #else
869 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
870 #endif
871 {
872 VPU_MSG_ERR("Force turn on HVD\n");
873 if(!HAL_VPU_EX_HVDInUsed())
874 {
875 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
876 {
877 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
878 {
879 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
880 return FALSE;
881 }
882 }
883 else
884 {
885 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
886 #ifdef CONFIG_MSTAR_CLKM
887 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
888 #else
889 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
890 #endif
891 }
892 }
893 else
894 {
895 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
896 }
897 }
898
899 //Check if we need to init HVD HW
900 #ifdef VDEC3
901 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
902 #else
903 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
904 #endif
905 {
906 if (!HAL_VPU_EX_MVDInUsed())
907 {
908 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
909 {
910 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
911 return FALSE;
912 }
913 }
914
915 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
916 {
917 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
918 return FALSE;
919 }
920 #if SUPPORT_MSVP9
921 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
922 {
923 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
924 }
925 #endif
926 }
927
928 #if SUPPORT_G2VP9 && defined(VDEC3)
929 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
930 {
931 if (!HAL_VPU_EX_MVDInUsed())
932 {
933 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
934 {
935 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
936 return FALSE;
937 }
938 }
939 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
940 {
941 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
942 return FALSE;
943 }
944 }
945 #endif
946
947 return TRUE;
948 }
949
_VPU_EX_InClock(MS_U32 u32type)950 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
951 {
952 switch (u32type)
953 {
954 case VPU_CLOCK_240MHZ:
955 return 240000000UL;
956 case VPU_CLOCK_216MHZ:
957 return 216000000UL;
958 case VPU_CLOCK_192MHZ:
959 return 192000000UL;
960 case VPU_CLOCK_12MHZ:
961 return 12000000UL;
962 case VPU_CLOCK_320MHZ:
963 return 320000000UL;
964 case VPU_CLOCK_288MHZ:
965 return 288000000UL;
966 case VPU_CLOCK_432MHZ:
967 return 432000000UL;
968 default:
969 return 384000000UL;
970 }
971 }
972
973
974 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
975 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)976 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
977 {
978 //#ifndef MSOS_TYPE_LINUX_KERNEL
979 #if 1
980 MS_U8 ClassNum = 0;
981 MBX_Result result;
982
983 #if 0
984 if (bVPUMbxInitFlag == TRUE)
985 {
986 return TRUE;
987 }
988 #endif
989
990 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
991 {
992 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
993 return FALSE;
994 }
995 else
996 {
997 MApi_MBX_Enable(TRUE);
998 }
999
1000 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
1001
1002 if (E_MBX_SUCCESS != result)
1003 {
1004 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
1005 return FALSE;
1006 }
1007
1008 result = MApi_MBX_RegisterMSG(ClassNum, 10);
1009
1010 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
1011 {
1012 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
1013 return FALSE;
1014 }
1015 else
1016 {
1017 bVPUMbxInitFlag = TRUE;
1018 u8VPUMbxMsgClass = ClassNum;
1019 return TRUE;
1020 }
1021 #else
1022 return FALSE;
1023 #endif
1024 }
1025
1026 //#ifdef MBX_2K
1027 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)1028 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
1029 {
1030 MBX_Result result;
1031 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
1032
1033 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1034 {
1035 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1036 }
1037
1038 if (bVPUMbxInitFlag == FALSE)
1039 {
1040 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1041 }
1042
1043 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1044 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1045 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1046 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1047 VPUReeToTeeMbxMsg.u8Index = msg_type;
1048
1049 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1050 if (E_MBX_SUCCESS != result)
1051 {
1052 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1053 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1054 }
1055
1056 // Receive Reply ACK from TEE side.
1057 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1058
1059 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1060
1061 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1062 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1063 {
1064 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1065 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1066 }
1067 else
1068 #else
1069 do
1070 {
1071 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1072 } while(E_MBX_SUCCESS != result);
1073 #endif
1074 {
1075 u8Index = VPUTeeToReeMbxMsg.u8Index;
1076 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1077
1078 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1079 {
1080 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1081 }
1082 }
1083
1084 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1085 }
1086 #endif
1087
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1088 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1089 {
1090 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1091 {
1092 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1093 {
1094 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1095 return FALSE;
1096 }
1097 else
1098 {
1099 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1100 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1101 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1102 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1103 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1104 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1105 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1106 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1107
1108 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1109
1110
1111 MS_U32 u32Start;
1112
1113 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1114 {
1115 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1116 pVPUHalContext->u32VPUSHMAddr = u32Start;
1117 }
1118 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1119 {
1120 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1121 pVPUHalContext->u32VPUSHMAddr = u32Start;
1122
1123 }
1124 else // == 0
1125 {
1126 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1127 }
1128 }
1129 }
1130 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1131 {
1132 MS_U32 u32Offset;
1133 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1134 {
1135 u32Offset = u32SHMAddr-u32MIU1Addr;
1136 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1137 }
1138 else
1139 {
1140 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1141 }
1142 }
1143 return TRUE;
1144 }
1145
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1146 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1147 {
1148 bVPUMbxInitFlag = TRUE;
1149 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1150 return TRUE;
1151 }
1152
1153 #endif
1154
HAL_VPU_EX_GetFWReload(void)1155 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1156 {
1157 return pVPUHalContext->bVpuExReloadFW;
1158 }
1159
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1160 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1161 {
1162 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1163 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1164 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1165 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1166 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1167 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1168 )
1169 {
1170 return FALSE;
1171 }
1172 else
1173 {
1174 return TRUE;
1175 }
1176 }
1177
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1178 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1179 {
1180 MS_PHY u32fwPA = NULL; //physical address
1181 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1182
1183 if (TRUE == HAL_VPU_EX_IsPowered())
1184 {
1185 VPU_MSG_DBG("IsPowered\n");
1186 return TRUE;
1187 }
1188 else
1189 {
1190 //VPU hold
1191 HAL_VPU_EX_SwRst(FALSE);
1192
1193 //VPU clock on
1194 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1195
1196 if (VPU_I_R_ON_MIU0)
1197 VPUInitParams.u8MiuSel = 0;
1198 else if (VPU_I_R_ON_MIU1)
1199 VPUInitParams.u8MiuSel = 1;
1200 else if (VPU_I_R_ON_MIU2)
1201 VPUInitParams.u8MiuSel = 2;
1202
1203 HAL_VPU_EX_Init(&VPUInitParams);
1204 }
1205
1206 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1207 VPU_EX_TaskInfo *pTaskInfo = NULL;
1208 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1209
1210 if (pInitPara)
1211 {
1212 pFWCodeCfg = pInitPara->pFWCodeCfg;
1213 pTaskInfo = pInitPara->pTaskInfo;
1214 pVlcCfg = pInitPara->pVLCCfg;
1215 }
1216 else
1217 {
1218 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1219 return FALSE;
1220 }
1221
1222 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1223 //#ifdef MBX_2K
1224 #if 1
1225 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1226 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1227 {
1228 SYS_TEEINFO teemode;
1229 MDrv_SYS_ReadKernelCmdLine();
1230 MDrv_SYS_GetTEEInfo(&teemode);
1231 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1232 {
1233 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1234
1235 if (FALSE == HAL_VPU_EX_GetFWReload())
1236 {
1237 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1238 {
1239 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1240 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1241 {
1242 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1243 return FALSE;
1244 }
1245 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1246 }
1247 else
1248 {
1249 //Check f/w prefix "VDEC30"
1250 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1251 {
1252 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1253 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1254 {
1255 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1256 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1257 return FALSE;
1258 }
1259 }
1260 else
1261 {
1262 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1263 }
1264 }
1265 }
1266 else
1267 {
1268 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1269 {
1270 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1271 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1272 return FALSE;
1273 }
1274 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1275 }
1276 }
1277 }
1278 else
1279 #endif
1280 #endif
1281 {
1282 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1283
1284 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1285 {
1286 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1287 return FALSE;
1288 }
1289 }
1290
1291 if (pVlcCfg)
1292 {
1293 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1294 {
1295 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1296 return FALSE;
1297 }
1298 }
1299
1300 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1301 {
1302 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1303 return FALSE;
1304 }
1305
1306 //Init HW
1307 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1308 {
1309 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1310 //_MVD_INIT_FAIL_RET();
1311 return FALSE;
1312 }
1313 else
1314 {
1315 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1316 }
1317
1318 //set vpu clock to FW
1319 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1320 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1321
1322 ctl_ptr->statue = CTL_STU_NONE;
1323 //notify controller the interface version of VPU driver.
1324 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1325 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1326 MsOS_FlushMemory();
1327 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1328
1329 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1330 if (TRUE == HAL_VPU_EX_IsRsted())
1331 {
1332 VPU_MSG_DBG("VPU_IsRsted\n");
1333 return TRUE;
1334 }
1335 else
1336 {
1337 HAL_VPU_EX_SwRstRelse();
1338 }
1339
1340 return TRUE;
1341 }
1342
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1343 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1344 {
1345 MS_BOOL bRet = FALSE;
1346 #if defined(VDEC3)
1347 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1348 #else
1349 MS_BOOL isEVD = FALSE ;
1350 #endif
1351 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1352 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1353 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1354
1355 if (FALSE == HAL_VPU_EX_MVDInUsed())
1356 {
1357 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1358 }
1359
1360 if (TRUE == isHVD)
1361 {
1362 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1363 }
1364
1365 #if defined(VDEC3)
1366 if (TRUE == isEVD)
1367 {
1368 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1369 }
1370 #endif
1371
1372 #if SUPPORT_G2VP9 && defined(VDEC3)
1373 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1374 {
1375 bRet = HAL_VP9_EX_DeinitHW();
1376 }
1377 #endif
1378 return bRet;
1379 }
1380
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1381 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1382 {
1383 HAL_VPU_EX_SwRst(TRUE);
1384 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1385 HAL_VPU_EX_DeInit();
1386
1387 return TRUE;
1388 }
1389
_VPU_EX_GetActiveCodecCnt(void)1390 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1391 {
1392 MS_U32 i;
1393 MS_U8 u8ActiveCnt = 0;
1394 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1395 {
1396 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1397 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1398 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1399 {
1400 u8ActiveCnt++;
1401 }
1402 }
1403 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1404 {
1405 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1406 }
1407 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1408 return u8ActiveCnt;
1409 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1410 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1411 {
1412 if (TRUE)
1413 {
1414 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1415 }
1416 else
1417 {
1418 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1419 }
1420 }
1421
_VPU_EX_ClockSpeed(MS_U32 u32type)1422 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1423 {
1424 switch (u32type)
1425 {
1426 case VPU_CLOCK_240MHZ:
1427 case VPU_CLOCK_216MHZ:
1428 case VPU_CLOCK_192MHZ:
1429 case VPU_CLOCK_12MHZ:
1430 case VPU_CLOCK_320MHZ:
1431 case VPU_CLOCK_288MHZ:
1432 case VPU_CLOCK_384MHZ:
1433 case VPU_CLOCK_432MHZ:
1434 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1435 break;
1436 default:
1437 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1438 break;
1439 }
1440 }
1441 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1442 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1443 {
1444 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1445 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1446 {
1447 return TRUE;
1448 }
1449 return FALSE;
1450 }
1451 #endif
1452
1453
1454 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1455 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1456 {
1457 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1458 {
1459 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1460 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1461 ms_VDECDecompressDeInit();
1462 return TRUE;
1463 }
1464 else
1465 {
1466 return FALSE;
1467 }
1468 }
1469 #endif
1470
1471 #if VPU_FIELD_DETECTOR
1472
1473 #include "FieldDetection.h"
1474
_HAL_VPU_EX_Field_Detecor_Task_HVD(MS_U32 u32Id)1475 static MS_BOOL _HAL_VPU_EX_Field_Detecor_Task_HVD(MS_U32 u32Id)
1476 {
1477 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1478 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1479 //VPU_FD_DispFrameInfo DispFrmInfo;
1480 MsOS_ReadMemory();
1481 //memset(&DispFrmInfo,0,sizeof(VPU_FD_DispFrameInfo));
1482
1483 if(pShm->u32CodecType == E_HVD_Codec_AVS)
1484 {
1485 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_FIELD_DETECT;
1486 }
1487
1488 while (1)
1489 {
1490 MsOS_DelayTask(1);
1491 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueWPtr];
1492 MS_U32 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
1493
1494 FrameInfo stFrameInfo;
1495 stFrameInfo.bFieldOrderSet = (pFrmInfo->u8ModeFlag & E_HVD_PP_FD_TOP_FIELD_FIRST)? 1:0;
1496 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32LumaAddr, stFrameInfo.phyBuffAddr);
1497 stFrameInfo.u16Height = pFrmInfo->u16Height;
1498 stFrameInfo.u16Width= pFrmInfo->u16Width;
1499 stFrameInfo.u32BuffSize = (pFrmInfo->u16Height)*(pFrmInfo->u16Width);
1500
1501 if(pShm->u32CodecType == E_HVD_Codec_AVS
1502 && pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_FIELD_DETECT_ONGOING)
1503 {
1504 if(pVPUHalContext->bFDInit[u8Offset]==FALSE)
1505 {
1506 FODInfo stFod;
1507 stFod.height =pFrmInfo->u16Height;
1508 stFod.width=pFrmInfo->u16Width;
1509 stFod.pitch=pFrmInfo->u16Pitch;
1510 stFod.tile_width = 16;
1511 stFod.tile_height= 32;
1512 VPU_MSG_INFO("Init Field Detector!!\n");
1513 InitFieldDetection(&stFod);
1514
1515 InitMemoryFromVPU(stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*20,
1516 stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*21,
1517 stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*22);
1518 pVPUHalContext->bFDInit[u8Offset] = TRUE;
1519 }
1520
1521 VPU_MSG_INFO("[%dx%d], [0x%x, 0x%x], %d ", stFrameInfo.u16Width, stFrameInfo.u16Height,
1522 (MS_U32)stFrameInfo.phyBuffAddr, (MS_U32)stFrameInfo.u32BuffSize, stFrameInfo.bFieldOrderSet);
1523
1524 MS_U32 u32Timer= MsOS_GetSystemTime();
1525 eIsFieldOrderInverse eResult = IsFieldOrderInverse(&stFrameInfo);
1526 VPU_MSG_INFO("[%dms] ", MsOS_GetSystemTime()-u32Timer);
1527 if(eResult == E_VDEC_IFOI_TRUE)
1528 {
1529 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_FIELD_DETECT_NEED_REVERSE;
1530 VPU_MSG_INFO("reverse=1\n");
1531 }
1532 else if(eResult == E_VDEC_IFOI_FALSE)
1533 {
1534 pShm->u8FrmPostProcSupport &= ~E_HVD_POST_PROC_FIELD_DETECT_NEED_REVERSE;
1535 VPU_MSG_INFO("reverse=0\n");
1536 }
1537
1538 pShm->u8FrmPostProcSupport &= ~E_HVD_POST_PROC_FIELD_DETECT_ONGOING;
1539
1540 MsOS_FlushMemory();
1541 }
1542 MsOS_ReadMemory();
1543
1544 }
1545
1546 return TRUE;
1547 }
1548
_HAL_VPU_EX_Field_Detecor_Task_MVD(MS_U32 u32Id)1549 static MS_BOOL _HAL_VPU_EX_Field_Detecor_Task_MVD(MS_U32 u32Id)
1550 {
1551 u32Id = u32Id;
1552 while(1)
1553 {
1554 MsOS_DelayTask(1);
1555 // TODO: handle MVD case here
1556 }
1557 return TRUE;
1558 }
1559
_HAL_VPU_EX_FdTask_Delete(MS_U32 u32Id,VPU_Hal_CTX * pVPUHalContext)1560 static void _HAL_VPU_EX_FdTask_Delete(MS_U32 u32Id, VPU_Hal_CTX* pVPUHalContext)
1561 {
1562 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1563 FInitFieldDetection();
1564 pVPUHalContext->bFDInit[u8Offset] = FALSE;
1565 MsOS_DeleteTask(pVPUHalContext->s32VpuFdTaskId[u8Offset]);
1566 pVPUHalContext->s32VpuFdTaskId[u8Offset] = -1;
1567 }
1568
1569
1570 #endif
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1571 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1572 {
1573 MS_BOOL bRet = TRUE;
1574 pVPUHalContext->_bVPUSingleMode = bEnable;
1575 return bRet;
1576 }
1577
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1578 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1579 {
1580 MS_BOOL bRet = TRUE;
1581 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1582 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1583 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1584
1585 return bRet;
1586 }
1587
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1588 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1589 {
1590 MS_BOOL bRet = TRUE;
1591 MS_U8 i=0;
1592 if (pstCfg != NULL)
1593 {
1594 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1595 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1596 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1597 {
1598 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1599 }
1600 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1601 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1602 }
1603 else
1604 {
1605 bRet = FALSE;
1606 }
1607 return bRet;
1608 }
1609
1610 //static MS_BOOL bVpuExReloadFW = TRUE;
1611 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1612 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1613 {
1614 pVPUHalContext->bVpuExReloadFW = bReload;
1615 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1616 return TRUE;
1617 }
1618
1619
1620 //-------------------------------------------------------------------------------------------------
1621 // Global Functions
1622 //-------------------------------------------------------------------------------------------------
1623 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1624 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1625 {
1626 #if HVD_ENABLE_RV_FEATURE
1627 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1628 {
1629 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1630 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1631 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1632
1633 if (pVlcCfg->u32BinSize)
1634 {
1635 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1636
1637 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1638 {
1639 cpyflag = E_SPIDMA_DEV_MIU1;
1640 }
1641 else
1642 {
1643 cpyflag = E_SPIDMA_DEV_MIU0;
1644 }
1645
1646 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1647 {
1648 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1649 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1650
1651 return FALSE;
1652 }
1653 }
1654 else
1655 {
1656 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1657 return FALSE;
1658 }
1659 #else
1660 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1661 return FALSE;
1662 #endif
1663 }
1664 else
1665 {
1666 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1667 {
1668 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1669 {
1670 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1671 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1672
1673 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1674 BDMA_Result bdmaRlt;
1675
1676 MsOS_FlushMemory();
1677 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1678
1679 if (E_BDMA_OK != bdmaRlt)
1680 {
1681 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1682 }
1683 #else
1684 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1685 #endif
1686 }
1687 else
1688 {
1689 VPU_MSG_ERR
1690 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1691 return FALSE;
1692 }
1693 }
1694 else
1695 {
1696 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1697 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1698 MS_U8 *pu8HVD_VLC_Binary;
1699
1700 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1701
1702 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1703 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1704 (MS_U32) sizeof(u8HVD_VLC_Binary));
1705
1706 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1707 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1708 #else
1709 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1710 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1711 (MS_U32) sizeof(u8HVD_VLC_Binary));
1712
1713 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1714 #endif
1715 #else
1716 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1717 return FALSE;
1718 #endif
1719 }
1720 }
1721 #endif
1722
1723 return TRUE;
1724 }
1725 #endif
1726 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1727 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1728 #else
1729 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1730 #endif
1731 {
1732 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1733 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1734 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1735 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1736 MS_U32 u32Arg = 0xFFFFFFFF;
1737 MS_U32 u32Timeout = 0;
1738 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1739 MS_U32 u32CmdArg = 0;
1740 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1741 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1742
1743 _HAL_VPU_Entry();
1744 //Check FW buffer size
1745 if (1 == u8Offset)
1746 {
1747 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1748 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1749
1750 if (u32CurFWBuffSize < u32MinFWBuffSize)
1751 {
1752 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1753 _HAL_VPU_Release();
1754 return FALSE;
1755 }
1756 }
1757
1758 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1759 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1760 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1761 {
1762 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1763 }
1764 #ifdef VDEC3
1765 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1766 #endif
1767
1768 if (0 == pVPUHalContext->u8TaskCnt)
1769 {
1770 //No task is created, need to load f/w, etc.
1771 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1772
1773 if (!_VPU_EX_InitAll(pInitPara))
1774 {
1775 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1776 _HAL_VPU_Release();
1777 return FALSE;
1778 }
1779
1780 //Check if controller finish initialization: clear mailbox, etc.
1781 //Need to check it before sending any controller commands!
1782 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1783 while (CTL_STU_NONE == ctl_ptr->statue)
1784 {
1785 if (HVD_GetSysTime_ms() > u32Timeout)
1786 {
1787 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1788 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1789 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1790 MS_U32 t=0;
1791 for (t=0; t<30; t++)
1792 {
1793 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1794 }
1795 _HAL_VPU_Release();
1796 return FALSE;
1797 }
1798
1799 MsOS_ReadMemory();
1800 }
1801
1802 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1803 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1804
1805 }
1806 else
1807 {
1808 if (pVPUHalContext->_bVPUSingleMode)
1809 {
1810 //Show error message
1811 printf("This task will use dram instead of sram!!!\n");
1812 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1813 }
1814
1815 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1816 {
1817 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1818 _HAL_VPU_Release();
1819 return FALSE;
1820 }
1821 if (pInitPara->pVLCCfg)
1822 {
1823 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1824 {
1825 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1826 _HAL_VPU_Release();
1827 return FALSE;
1828 }
1829 }
1830 }
1831
1832
1833 #ifdef VDEC3
1834 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1835 {
1836 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1837
1838 memset(pTemp4,0,sizeof(VDEC_VBBU));
1839
1840 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1841
1842 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1843
1844 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1845
1846 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1847
1848 memset(pTemp2,0,sizeof(CMD_QUEUE));
1849
1850 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1851
1852 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1853
1854 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1855
1856 memset(pTemp3,0,0x2000);
1857
1858 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1859
1860 memset((void*)pVersion,0,0x8);
1861
1862 *pVersion = 1; //0:diu, 1:wb
1863 }
1864
1865 #endif
1866
1867 #if 1 // For TEE
1868 #ifdef VDEC3
1869 #if SUPPORT_G2VP9
1870 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1871 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1872 #else
1873 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1874 #endif
1875 #else
1876 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1877 #endif
1878 {
1879 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1880
1881 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1882 {
1883 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1884 }
1885 else
1886 {
1887 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1888 }
1889
1890 MsOS_FlushMemory();
1891 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1892
1893 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1894 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1895 }
1896 #endif
1897
1898 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1899 {
1900 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1901 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1902
1903 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1904
1905 MsOS_FlushMemory();
1906 }
1907
1908 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1909 {
1910 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1911 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1912 {
1913 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1914 }
1915 }
1916
1917 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1918 {
1919 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1920 //arg=1 to get better performance for single task
1921 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1922 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1923 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1924 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1925 {
1926 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1927 }
1928 }
1929 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1930 {
1931 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1932 {
1933 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1934 {
1935 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1936 u32CmdArg = CTL_MODE_3DTV;
1937 break;
1938 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1939 u32CmdArg = CTL_MODE_3DTV_PROG;
1940 break;
1941 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1942 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1943 break;
1944 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1945 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1946 break;
1947 default:
1948 u32CmdArg = CTL_MODE_3DTV;
1949 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1950 break;
1951 }
1952 }
1953 else
1954 {
1955 u32CmdArg = CTL_MODE_3DWMV;
1956 }
1957 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1958 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1959 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1960 {
1961 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1962 }
1963 }
1964 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1965 {
1966 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1967 {
1968 u32CmdArg = CTL_MODE_ONE_STC;
1969 }
1970 else
1971 {
1972 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1973 }
1974 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1975 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1976 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1977 {
1978 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1979 }
1980 }
1981
1982 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1983 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1984 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1985 #ifdef VDEC3
1986 {
1987 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1988 }
1989 #else
1990 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1991 #endif
1992
1993 #ifdef VDEC3
1994 #if SUPPORT_G2VP9
1995 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1996 #else
1997 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1998 #endif
1999 {
2000 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2001 }
2002 #else
2003 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2004 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
2005 #endif
2006 else
2007 {
2008 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2009 _HAL_VPU_Release();
2010 return FALSE;
2011 }
2012 #else
2013 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
2014 #endif
2015
2016 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
2017 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
2018
2019 MsOS_ReadMemory();
2020 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2021 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2022
2023 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2024 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2025 {
2026 if (HVD_GetSysTime_ms() > u32Timeout)
2027 {
2028 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2029 MS_U32 t=0;
2030 for (t=0; t<30; t++)
2031 {
2032 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
2033 }
2034 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2035 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2036 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2037 _HAL_VPU_Release();
2038 return FALSE;
2039 //#endif
2040 }
2041
2042 MsOS_ReadMemory();
2043 }
2044
2045 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2046 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2047
2048 #ifdef VDEC3
2049 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2050 #else
2051 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2052 #endif
2053 {
2054 HAL_HVD_EX_SetNalTblAddr(u32Id);
2055 }
2056
2057 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2058 {
2059 eDecType = E_VPU_EX_DECODER_MVD;
2060 }
2061 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2062 {
2063 eDecType = E_VPU_EX_DECODER_HVD;
2064 }
2065 #ifdef VDEC3
2066 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2067 {
2068 eDecType = E_VPU_EX_DECODER_EVD;
2069 }
2070 #if SUPPORT_G2VP9
2071 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2072 {
2073 eDecType = E_VPU_EX_DECODER_G2VP9;
2074 }
2075 #endif
2076 #endif
2077 else
2078 {
2079 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2080 _HAL_VPU_Release();
2081 return FALSE;
2082 }
2083
2084 #ifdef VDEC3
2085 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
2086 {
2087 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2088 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2089 }
2090 #endif
2091
2092 if (pTaskInfo->eDecType != eDecType)
2093 {
2094 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2095 pTaskInfo->eDecType, eDecType);
2096 }
2097 goto _SAVE_DEC_TYPE;
2098
2099 _SAVE_DEC_TYPE:
2100 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2101 {
2102 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
2103 }
2104 else
2105 {
2106 VPU_MSG_ERR("Cannot save eDecType!!\n");
2107 }
2108
2109 #if VPU_FIELD_DETECTOR
2110 if(pVPUHalContext->s32VpuFdTaskId[0] == -1 && pVPUHalContext->s32VpuFdTaskId[1] == -1
2111 && pVPUHalContext->s32VpuFdTaskId[2] == -1 && pVPUHalContext->s32VpuFdTaskId[3] == -1
2112 && pVPUHalContext->s32VpuFdTaskId[4] == -1 && pVPUHalContext->s32VpuFdTaskId[5] == -1
2113 && pVPUHalContext->s32VpuFdTaskId[6] == -1 && pVPUHalContext->s32VpuFdTaskId[7] == -1
2114 && pVPUHalContext->s32VpuFdTaskId[8] == -1 && pVPUHalContext->s32VpuFdTaskId[9] == -1
2115 && pVPUHalContext->s32VpuFdTaskId[10] == -1 && pVPUHalContext->s32VpuFdTaskId[11] == -1
2116 && pVPUHalContext->s32VpuFdTaskId[12] == -1 && pVPUHalContext->s32VpuFdTaskId[13] == -1
2117 && pVPUHalContext->s32VpuFdTaskId[14] == -1 && pVPUHalContext->s32VpuFdTaskId[15] == -1
2118 )
2119 {
2120 MS_S32 s32VPUFDTaskId = -1;
2121 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2122 {
2123 s32VPUFDTaskId = MsOS_CreateTask((TaskEntry)_HAL_VPU_EX_Field_Detecor_Task_MVD,
2124 u32Id,
2125 E_TASK_PRI_MEDIUM,
2126 TRUE,
2127 NULL,
2128 32, // stack size..
2129 "VPU_FieldDetector_MVD_task");
2130 }
2131 else if(E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType ||E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2132 {
2133 VPU_MSG_INFO(" Create _HAL_VPU_EX_Field_Detecor_Task_HVD()\n");
2134 s32VPUFDTaskId = MsOS_CreateTask((TaskEntry)_HAL_VPU_EX_Field_Detecor_Task_HVD,
2135 u32Id,
2136 E_TASK_PRI_MEDIUM,
2137 TRUE,
2138 NULL,
2139 32, // stack size..
2140 "VPU_FieldDetector_HVD_task");
2141 }
2142 if (s32VPUFDTaskId < 0)
2143 {
2144 VPU_MSG_ERR("Field Detector Task create failed\n");
2145 }
2146 else
2147 {
2148 pVPUHalContext->s32VpuFdTaskId[u8Offset]= s32VPUFDTaskId;
2149 }
2150
2151 }
2152 #endif
2153
2154 (pVPUHalContext->u8TaskCnt)++;
2155 _HAL_VPU_Release();
2156 return TRUE;
2157 }
2158
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2159 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2160 {
2161 HVD_Return eRet;
2162 #ifdef VDEC3
2163 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2164 #else
2165 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2166 #endif
2167 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2168 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2169
2170 _HAL_VPU_Entry();
2171 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2172
2173 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2174 if(eRet != E_HVD_RETURN_SUCCESS)
2175 {
2176 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2177 }
2178
2179 {
2180 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2181 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2182 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2183
2184 MsOS_ReadMemory();
2185
2186 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2187 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2188
2189 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2190 {
2191 if (HVD_GetSysTime_ms() > u32Timeout)
2192 {
2193 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2194 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2195 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2196
2197 if(pVPUHalContext->u8TaskCnt == 1)
2198 {
2199 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2200 break;
2201 }
2202 else if(pVPUHalContext->u8TaskCnt == 2)
2203 {
2204 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2205 break;
2206 }
2207 else
2208 {
2209 VPU_MSG_ERR("Task number is not correct\n");
2210 _HAL_VPU_Release();
2211 return FALSE;
2212 }
2213 }
2214
2215 MsOS_ReadMemory();
2216 }
2217
2218 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2219 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2220 }
2221 #if SUPPORT_EVD
2222 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2223 {
2224 HAL_EVD_EX_ClearTSPInput(u32Id);
2225 }
2226 #endif
2227
2228 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2229 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2230 {
2231 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2232 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2233 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2234 }
2235
2236 #if VPU_FIELD_DETECTOR
2237 _HAL_VPU_EX_FdTask_Delete(u32Id, pVPUHalContext);
2238 #endif
2239
2240 if (pVPUHalContext->u8TaskCnt)
2241 {
2242 (pVPUHalContext->u8TaskCnt)--;
2243 }
2244 else
2245 {
2246 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2247 }
2248
2249 if (0 == pVPUHalContext->u8TaskCnt)
2250 {
2251 int i;
2252 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2253 _VPU_EX_DeinitAll(pInitPara);
2254 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2255 pVPUHalContext->u32VPUSHMAddr = 0;
2256
2257 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2258 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2259 }
2260 else
2261 {
2262 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2263 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2264 }
2265
2266 _HAL_VPU_Release();
2267 return TRUE;
2268 }
2269
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2270 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2271 {
2272 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2273 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2274 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2275 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2276 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2277 #endif
2278
2279 if (FALSE == HAL_VPU_EX_GetFWReload())
2280 {
2281 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2282 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2283 {
2284 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2285 }
2286 else
2287 {
2288 //Check f/w prefix "VDEC30"
2289 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2290 {
2291 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2292 }
2293 else
2294 {
2295 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2296 return TRUE;
2297 }
2298 }
2299 }
2300
2301 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2302 {
2303 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2304 if (u32Size != 0)
2305 {
2306 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2307
2308
2309 MS_U32 u32Start;
2310 MS_U32 u32StartOffset;
2311 MS_U8 u8MiuSel;
2312
2313 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2314
2315
2316 if(u8MiuSel == E_CHIP_MIU_0)
2317 cpyflag = E_SPIDMA_DEV_MIU0;
2318 else if(u8MiuSel == E_CHIP_MIU_1)
2319 cpyflag = E_SPIDMA_DEV_MIU1;
2320 else if(u8MiuSel == E_CHIP_MIU_2)
2321 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2322
2323 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2324 {
2325 goto _load_code_fail;
2326 }
2327 }
2328 else
2329 {
2330 goto _load_code_fail;
2331 }
2332 #else
2333 goto _load_code_fail;
2334 #endif
2335 }
2336 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2337 {
2338 if (u32BinAddr != 0 && u32Size != 0)
2339 {
2340 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2341 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2342 {
2343 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2344 {
2345 VPU_MSG_INFO("Decompress ok!!!\n");
2346 }
2347 else
2348 {
2349 VPU_MSG_INFO("Decompress fail!!!\n");
2350 }
2351 }
2352 else
2353 #endif
2354 {
2355 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2356 }
2357 }
2358 else
2359 {
2360 goto _load_code_fail;
2361 }
2362 }
2363 else
2364 {
2365 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2366 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2367 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2368 (MS_U32) sizeof(u8HVD_FW_Binary));
2369
2370 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2371 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2372 {
2373 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2374 {
2375 VPU_MSG_INFO("Decompress ok!!!\n");
2376 }
2377 else
2378 {
2379 VPU_MSG_INFO("Decompress fail!!!\n");
2380 }
2381 }
2382 else
2383 #endif
2384 {
2385 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2386 }
2387 #else
2388 goto _load_code_fail;
2389 #endif
2390 }
2391
2392 MAsm_CPU_Sync();
2393 MsOS_FlushMemory();
2394
2395 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2396 {
2397 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2398 goto _load_code_fail;
2399 }
2400
2401 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2402 return TRUE;
2403
2404 _load_code_fail:
2405 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2406 return FALSE;
2407 }
2408
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2409 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2410 {
2411 u32VPURegOSBase = u32RegBase;
2412 }
2413
HAL_VPU_EX_Init_Share_Mem(void)2414 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2415 {
2416 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2417
2418 MS_U32 u32ShmId;
2419 MS_VIRT u32Addr;
2420 MS_U32 u32BufSize;
2421
2422
2423 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2424 sizeof(VPU_Hal_CTX),
2425 &u32ShmId,
2426 &u32Addr,
2427 &u32BufSize,
2428 MSOS_SHM_QUERY))
2429 {
2430 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2431 sizeof(VPU_Hal_CTX),
2432 &u32ShmId,
2433 &u32Addr,
2434 &u32BufSize,
2435 MSOS_SHM_CREATE))
2436 {
2437 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2438 if(pVPUHalContext == NULL)
2439 {
2440 pVPUHalContext = &gVPUHalContext;
2441 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2442 _VPU_EX_Context_Init();
2443 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2444 }
2445 else
2446 {
2447 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2448 }
2449 //return FALSE;
2450 }
2451 else
2452 {
2453 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2454 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2455 _VPU_EX_Context_Init();
2456 }
2457 }
2458 else
2459 {
2460 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2461 }
2462 #else
2463 if(pVPUHalContext == NULL)
2464 {
2465 pVPUHalContext = &gVPUHalContext;
2466 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2467 _VPU_EX_Context_Init();
2468 }
2469 #endif
2470
2471 return TRUE;
2472
2473 }
2474
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2475 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2476 {
2477 MS_U32 i = 0;
2478
2479 _HAL_VPU_MutexCreate();
2480
2481 _HAL_VPU_Entry();
2482
2483 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2484 {
2485 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2486 {
2487 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2488 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2489 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2490 _HAL_VPU_Release();
2491 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2492 }
2493 }
2494 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2495 {
2496 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2497 {
2498 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2499 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2500 {
2501 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2502 _HAL_VPU_Release();
2503 return pVPUHalContext->_stVPUStream[i].eStreamId;
2504 }
2505 }
2506 }
2507 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2508 {
2509 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2510 {
2511 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2512 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2513 {
2514 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2515 _HAL_VPU_Release();
2516 return pVPUHalContext->_stVPUStream[i].eStreamId;
2517 }
2518 }
2519 }
2520 #ifdef VDEC3
2521 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2522 {
2523 #if 1 // bound FW task to main/sub stream
2524 i = eStreamType - E_HAL_VPU_N_STREAM;
2525 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2526 {
2527 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2528 _HAL_VPU_Release();
2529 return pVPUHalContext->_stVPUStream[i].eStreamId;
2530 }
2531 #else // dynamic select FW task id
2532 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2533 {
2534 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2535 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2536 {
2537 return pVPUHalContext->_stVPUStream[i].eStreamId;
2538 }
2539 }
2540 #endif
2541 }
2542 #endif
2543
2544 _HAL_VPU_Release();
2545
2546 return E_HAL_VPU_STREAM_NONE;
2547 }
2548
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2549 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2550 {
2551 _HAL_VPU_Entry();
2552
2553 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2554 {
2555 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2556 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2557 }
2558 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2559 {
2560 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2561 }
2562
2563 _HAL_VPU_Release();
2564
2565 return TRUE;
2566 }
2567
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2568 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2569 {
2570 MS_U8 u8Idx = 0;
2571
2572 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2573
2574 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2575 {
2576 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2577 {
2578 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2579 return 0;
2580 }
2581 }
2582 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2583 {
2584 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2585 {
2586 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2587 return 1;
2588 }
2589 }
2590
2591 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2592 {
2593 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2594 break;
2595 }
2596
2597 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2598 {
2599 VPU_MSG_ERR("all vpu free streams are occupied \n");
2600 return 0xFF;
2601 }
2602
2603 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2604 return u8Idx;
2605 }
2606
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2607 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2608 {
2609 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2610
2611 // enable module
2612 _VPU_EX_ClockInv(InitParams->bClockInv);
2613 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2614 HAL_VPU_EX_PowerCtrl(TRUE);
2615
2616 #ifdef CONFIG_MSTAR_CLKM
2617 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2618 #endif
2619
2620 #ifdef CONFIG_MSTAR_SRAMPD
2621 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2622 HVD_Delay_ms(1);
2623 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2624 HVD_Delay_ms(1);
2625 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2626 HVD_Delay_ms(1);
2627 #endif
2628 #if 1 //Create VPU's own mutex
2629 //_HAL_VPU_MutexCreate();
2630 #else
2631 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2632 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2633 #endif
2634
2635 return TRUE;
2636 }
2637
HAL_VPU_EX_DeInit(void)2638 MS_BOOL HAL_VPU_EX_DeInit(void)
2639 {
2640 if (0 != _VPU_EX_GetActiveCodecCnt())
2641 {
2642 VPU_MSG_DBG("do nothing since codec is active.\n");
2643 return TRUE;
2644 }
2645
2646 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2647
2648 #ifdef CONFIG_MSTAR_CLKM
2649 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2650 #else
2651 HAL_VPU_EX_PowerCtrl(FALSE);
2652 #endif
2653
2654 #ifdef CONFIG_MSTAR_SRAMPD
2655 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2656 HVD_Delay_ms(1);
2657 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2658 HVD_Delay_ms(1);
2659 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2660 HVD_Delay_ms(1);
2661 #endif
2662
2663 HAL_VPU_EX_SwRelseMAU();
2664 //_HAL_VPU_MutexDelete();
2665
2666 return TRUE;
2667 }
2668
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2669 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2670 {
2671 if (bEnable)
2672 {
2673 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2674 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2675 pVPUHalContext->_bVPUPowered = TRUE;
2676 }
2677 else
2678 {
2679 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2680 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2681 pVPUHalContext->_bVPUPowered = FALSE;
2682 }
2683 }
2684
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2685 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2686 {
2687 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2688 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2689 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2690 VPU_EX_TimerDelayMS(1);
2691 }
2692
2693 ///-----------------------------------------------------------------------------
2694 /// config AVCH264 CPU
2695 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2696 /// @param u8dlend_en \b IN: endian
2697 /// - 1, little endian
2698 /// - 0, big endian
2699 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2700 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2701 {
2702 MS_BOOL bRet = TRUE;
2703 MS_U32 u32Offset = 0;
2704 MS_U16 tempreg = 0;
2705 MS_U8 u8MiuSel;
2706 //MS_U32 u32TmpStartOffset;
2707
2708 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2709
2710 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2711 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2712 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2713 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2714 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2715 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2716 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2717 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2718 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2719 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2720
2721 #if (HVD_ENABLE_IQMEM)
2722 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2723 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2724 #endif
2725
2726 #if (VPU_FORCE_MIU_MODE)
2727 // Data sram base Unit: byte address
2728 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2729 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2730 // Instruction sram base Unit: byte address
2731 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2732 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2733
2734 #ifndef HAL_FEATURE_MAU
2735 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2736 #endif
2737 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2738
2739 //use force miu mode
2740 if(u8MiuSel == E_CHIP_MIU_0)
2741 {
2742 #ifdef HAL_FEATURE_MAU
2743 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2744 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2745 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2746 #else
2747 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2748 #endif
2749 }
2750 else if(u8MiuSel == E_CHIP_MIU_1)
2751 {
2752 #ifdef HAL_FEATURE_MAU
2753 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2754 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2755 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2756 #else
2757 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2758 #endif
2759 }
2760 else //miu 2
2761 {
2762 #ifdef HAL_FEATURE_MAU
2763 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2764 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2765 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2766 #else
2767 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2768 #endif
2769 }
2770 #else
2771 ///TODO:
2772 #endif
2773
2774
2775 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2776 tempreg |= VPU_REG_IO2_EN;
2777 tempreg |= VPU_REG_QMEM_SPACE_EN;
2778 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2779
2780 return bRet;
2781 }
2782
2783 ///-----------------------------------------------------------------------------
2784 /// Set IQMem data access mode or instruction fetch mode
2785 /// @param u8dlend_en \b IN: endian
2786 /// - 1, switch to data access mode
2787 /// - 0, switch to instruction fetch mode
2788 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2789 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2790 {
2791
2792 if(bEnable){
2793
2794 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2795 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2796
2797 }
2798 else{
2799
2800 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2801
2802 }
2803 }
2804
2805 ///-----------------------------------------------------------------------------
2806 /// H.264 SW reset
2807 /// @return TRUE or FALSE
2808 /// - TRUE, Success
2809 /// - FALSE, Failed
2810 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2811 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2812 {
2813 MS_U16 tempreg = 0, tempreg1 = 0;
2814 MS_U16 idle_cnt;
2815 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2816 tempreg |= VPU_REG_CPU_STALL_EN;
2817 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2818
2819 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2820 // 0xf means VPU is not stalled
2821 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2822 pVPUHalContext->u8ForceRst = 0;
2823 // write R2 RIU registers to select DCU/ICU debug data
2824 // Writing these registers here provides enough time for them to
2825 // take effect.
2826 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2827 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2828 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2829 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2830
2831 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2832 // This step is important because in the next step we want to make
2833 // sure "DCU is not replaying when R2 is stalled".
2834 idle_cnt = 100;
2835 do
2836 {
2837 if (--idle_cnt == 0)
2838 {
2839 printf("VPU_REG_CPU_STALL_EN is not set\n");
2840 break;
2841 }
2842 MsOS_DelayTask(1);
2843 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2844 // check CPU status: DCU should NOT be replaying
2845 // If R2 has been stalled, we can guarantee that if we found DCU is
2846 // NOT replaying, it will NOT replay later even CPU is going to issue
2847 // a load/store instruction.
2848 idle_cnt = 100;
2849 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2850 {
2851 if (--idle_cnt == 0)
2852 {
2853 printf("DCU is replaying\n");
2854 break;
2855 }
2856 MsOS_DelayTask(1);
2857 }
2858 // wait 1ms to prevent race condition between (1) DCU is not
2859 // replaying, and (2) BIU start to doing new job or ICU start to
2860 // fetch new instruction
2861 MsOS_DelayTask(1);
2862
2863 // check BIU should be empty
2864 idle_cnt = 100;
2865 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2866 {
2867 if (--idle_cnt == 0)
2868 {
2869 printf("BIU DCU idle time out~~~~~\n");
2870 break;
2871 }
2872 MsOS_DelayTask(1);
2873 }
2874
2875 // check CPU is not requesting ICU
2876 idle_cnt = 100;
2877 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2878 {
2879 if (--idle_cnt == 0)
2880 {
2881 printf("CPU keeps requesting ICU\n");
2882 break;
2883 }
2884 MsOS_DelayTask(1);
2885 }
2886
2887 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2888 // (2) ISB start to fetch
2889 MsOS_DelayTask(1);
2890
2891 // check ISB should be idle
2892 idle_cnt = 100;
2893 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2894 {
2895 if (--idle_cnt == 0)
2896 {
2897 printf("ISB is busy\n");
2898 break;
2899 }
2900 MsOS_DelayTask(1);
2901 }
2902 }
2903 #ifdef HAL_FEATURE_MAU
2904 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2905 if (bCheckMauIdle)
2906 {
2907 MS_U32 mau_idle_cnt = 100;// ms
2908 while (mau_idle_cnt)
2909 {
2910 if (TRUE == _VPU_EX_MAU_IDLE())
2911 {
2912 break;
2913 }
2914 mau_idle_cnt--;
2915 MsOS_DelayTask(1);
2916 }
2917
2918 if (mau_idle_cnt == 0)
2919 {
2920 printf("MAU idle time out~~~~~\n");
2921 }
2922 }
2923 #endif
2924
2925 // this command set MIU to block R2 (does not ack R2's request)
2926 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2927
2928 #ifdef HAL_FEATURE_MAU
2929 // reset MAU
2930 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2931 tempreg1 |= MAU1_REG_SW_RESET;
2932 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2933 #if defined(UDMA_FPGA_ENVI)
2934 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2935 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2936 #endif
2937 #endif
2938
2939 // reset R2
2940 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2941 // by the same RIU write, the R2 reset signal may reach afifo eralier
2942 // than MIU reset and afifo write pointer will be reset to position 0.
2943 // In this case, afifo consider it is not empty because read/write
2944 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2945 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2946 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2947 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2948 VPU_EX_TimerDelayMS(1);
2949 tempreg &= ~VPU_REG_CPU_R2_EN;
2950 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2951 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2952
2953 VPU_EX_TimerDelayMS(1);
2954
2955 // this command set MIU to accept R2 (can ack R2's request)
2956 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2957
2958 pVPUHalContext->_bVPURsted = FALSE;
2959 return TRUE;
2960 }
2961 /*
2962 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2963 {
2964 MS_U16 tempreg = 0, tempreg1 = 0;
2965 #ifndef HAL_FEATURE_MAU
2966 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2967 tempreg |= VPU_REG_CPU_STALL_EN;
2968 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2969
2970 MS_U32 idle_cnt = 100;// ms
2971 while (idle_cnt)
2972 {
2973 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2974 {
2975 break;
2976 }
2977 idle_cnt--;
2978 MsOS_DelayTask(1);
2979 }
2980
2981 if (idle_cnt == 0)
2982 {
2983 printf("ISB ICU idle time out~~~~~\n");
2984 }
2985
2986 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2987 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2988 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2989 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2990
2991 MS_U32 idle_cnt_1 = 100;// ms
2992 while (idle_cnt_1)
2993 {
2994 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2995 {
2996 break;
2997 }
2998 idle_cnt_1--;
2999 MsOS_DelayTask(1);
3000 }
3001
3002 if (idle_cnt_1 == 0)
3003 {
3004 printf("BIU DCU idle time out~~~~~\n");
3005 }
3006
3007 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3008 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3009 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3010 VPU_EX_TimerDelayMS(1);
3011 tempreg &= ~VPU_REG_CPU_R2_EN;
3012 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3013 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3014
3015 #else
3016 //MAU has been removed since manhattan, so it is not necessary to check MAU status
3017
3018 if (bCheckMauIdle)
3019 {
3020 MS_U32 mau_idle_cnt = 100;// ms
3021 while (mau_idle_cnt)
3022 {
3023 if (TRUE == _VPU_EX_MAU_IDLE())
3024 {
3025 break;
3026 }
3027 mau_idle_cnt--;
3028 MsOS_DelayTask(1);
3029 }
3030
3031 if (mau_idle_cnt == 0)
3032 {
3033 printf("MAU idle time out~~~~~\n");
3034 }
3035 }
3036
3037
3038 HAL_VPU_EX_MIU_RW_Protect(TRUE);
3039
3040 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3041 tempreg1 |= MAU1_REG_SW_RESET;
3042 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3043
3044 #if defined(UDMA_FPGA_ENVI)
3045 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3046 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3047 #endif
3048
3049 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3050 tempreg &= ~VPU_REG_CPU_R2_EN;
3051 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3052 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3053 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3054 #endif
3055 VPU_EX_TimerDelayMS(1);
3056 HAL_VPU_EX_MIU_RW_Protect(FALSE);
3057
3058 pVPUHalContext->_bVPURsted = FALSE;
3059 return TRUE;
3060 }
3061 */
3062 ///-----------------------------------------------------------------------------
3063 /// CPU reset release
3064 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)3065 void HAL_VPU_EX_SwRstRelse(void)
3066 {
3067 MS_U16 tempreg = 0;
3068
3069 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
3070 tempreg &= ~VPU_REG_CPU_STALL_EN;
3071 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
3072
3073 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3074 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3075 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3076 VPU_EX_TimerDelayMS(1);
3077 tempreg |= VPU_REG_CPU_SW_RSTZ;
3078 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3079 VPU_EX_TimerDelayMS(1);
3080 tempreg |= VPU_REG_CPU_R2_EN;
3081 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3082 #ifdef HAL_FEATURE_MAU
3083 MS_U16 tempreg1 = 0;
3084 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3085 tempreg1 &= ~MAU1_REG_SW_RESET;
3086 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3087 #endif
3088 pVPUHalContext->_bVPURsted = TRUE;
3089 }
3090
HAL_VPU_EX_SwRelseMAU(void)3091 void HAL_VPU_EX_SwRelseMAU(void)
3092 {
3093
3094 #ifdef HAL_FEATURE_MAU
3095 MS_U16 tempreg = 0;
3096 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
3097 tempreg &= ~MAU1_REG_SW_RESET;
3098 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
3099 #endif
3100 }
3101
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3102 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3103 {
3104 MS_U32 u32value = 0;
3105
3106 return u32value;
3107 }
3108
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3109 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3110 {
3111 MS_BOOL bRet = TRUE;
3112
3113 return bRet;
3114 }
3115
3116 ///-----------------------------------------------------------------------------
3117 /// Check AVCH264 Ready or not
3118 /// @return TRUE or FALSE
3119 /// - TRUE, MailBox is free
3120 /// - FALSE, MailBox is busy
3121 /// @param u8MBox \b IN: MailBox to check
3122 /// - AVCH264_HI_MBOX0,
3123 /// - AVCH264_HI_MBOX1,
3124 /// - AVCH264_RISC_MBOX0,
3125 /// - AVCH264_RISC_MBOX1,
3126 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)3127 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
3128 {
3129 MS_BOOL bResult = FALSE;
3130
3131 switch (u32type)
3132 {
3133 case VPU_HI_MBOX0:
3134 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3135 break;
3136 case VPU_HI_MBOX1:
3137 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3138 break;
3139 case VPU_RISC_MBOX0:
3140 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3141 break;
3142 case VPU_RISC_MBOX1:
3143 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3144 break;
3145 default:
3146 break;
3147 }
3148 return bResult;
3149 }
3150
3151
3152 ///-----------------------------------------------------------------------------
3153 /// Read message from AVCH264
3154 /// @return TRUE or FALSE
3155 /// - TRUE, success
3156 /// - FALSE, failed
3157 /// @param u8MBox \b IN: MailBox to read
3158 /// - AVCH264_RISC_MBOX0
3159 /// - AVCH264_RISC_MBOX1
3160 /// @param u32Msg \b OUT: message read
3161 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)3162 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
3163 {
3164 MS_BOOL bResult = TRUE;
3165
3166 switch (u32type)
3167 {
3168 case VPU_HI_MBOX0:
3169 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3170 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3171 break;
3172 case VPU_HI_MBOX1:
3173 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3174 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3175 break;
3176 case VPU_RISC_MBOX0:
3177 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3178 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3179 break;
3180 case VPU_RISC_MBOX1:
3181 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3182 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3183 break;
3184 default:
3185 *u32Msg = 0;
3186 bResult = FALSE;
3187 break;
3188 }
3189 return bResult;
3190 }
3191
3192 ///-----------------------------------------------------------------------------
3193 /// Mailbox from AVCH264 clear bit resest
3194 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3195 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3196 {
3197 switch (u32type)
3198 {
3199 case VPU_RISC_MBOX0:
3200 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3201 break;
3202 case VPU_RISC_MBOX1:
3203 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3204 break;
3205 default:
3206 break;
3207 }
3208 }
3209
3210 ///-----------------------------------------------------------------------------
3211 /// Send message to AVCH264
3212 /// @return TRUE or FALSE
3213 /// - TRUE, Success
3214 /// - FALSE, Failed
3215 /// @param u8MBox \b IN: MailBox
3216 /// - AVCH264_HI_MBOX0,
3217 /// - AVCH264_HI_MBOX1,
3218 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3219 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3220 {
3221 MS_BOOL bResult = TRUE;
3222
3223 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3224
3225 switch (u32type)
3226 {
3227 case VPU_HI_MBOX0:
3228 {
3229 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3230 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3231 break;
3232 }
3233 case VPU_HI_MBOX1:
3234 {
3235 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3236 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3237 break;
3238 }
3239 default:
3240 {
3241 bResult = FALSE;
3242 break;
3243 }
3244 }
3245
3246 return bResult;
3247 }
3248
HAL_VPU_EX_GetProgCnt(void)3249 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3250 {
3251
3252 MS_U16 expc_l=0;
3253 MS_U16 expc_h=0;
3254 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3255 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3256 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3257 }
3258
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3259 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3260 {
3261 return _VPU_EX_GetOffsetIdx(u32Id);
3262 }
3263
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3264 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3265 {
3266 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3267
3268 if (u32ShmAddr == 0)
3269 {
3270 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3271 }
3272 else
3273 {
3274 if (u8Offset == 0)
3275 {
3276 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3277 }
3278 else if (u8Offset == 1)
3279 {
3280 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3281 }
3282 }
3283
3284 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3285 return;
3286 }
3287
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3288 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3289 {
3290 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3291
3292 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3293 }
3294
3295 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3296 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3297 {
3298 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3299 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3300 MS_VIRT VsyncBridgeOffset = 0;
3301
3302 if (VPUSHMAddr != 0) // TEE project
3303 {
3304 if ((u8Offset == 0) || (u8Offset == 1))
3305 {
3306 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3307 }
3308 else
3309 {
3310 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3311 }
3312 }
3313 else // normal project
3314 {
3315 if ((u8Offset == 0) || (u8Offset == 1))
3316 {
3317 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3318 }
3319 else
3320 {
3321 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3322 }
3323 }
3324
3325 return VsyncBridgeOffset;
3326 }
3327
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3328 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3329 {
3330 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3331 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3332 MS_VIRT VsyncBridgeExtOffset = 0;
3333
3334 if (VPUSHMAddr != 0) // TEE project
3335 {
3336 if ((u8Offset == 0) || (u8Offset == 1))
3337 {
3338 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3339 }
3340 else
3341 {
3342 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3343 }
3344 }
3345 else // normal project
3346 {
3347 if ((u8Offset == 0) || (u8Offset == 1))
3348 {
3349 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3350 }
3351 else
3352 {
3353 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3354 }
3355 }
3356
3357 return VsyncBridgeExtOffset;
3358 }
3359 #endif
3360
HAL_VPU_EX_IsPowered(void)3361 MS_BOOL HAL_VPU_EX_IsPowered(void)
3362 {
3363 return pVPUHalContext->_bVPUPowered;
3364 }
3365
HAL_VPU_EX_IsRsted(void)3366 MS_BOOL HAL_VPU_EX_IsRsted(void)
3367 {
3368 return pVPUHalContext->_bVPURsted;
3369 }
3370
HAL_VPU_EX_IsEVDR2(void)3371 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3372 {
3373 #ifdef EVDR2
3374 return TRUE;
3375 #else
3376 return FALSE;
3377 #endif
3378 }
3379
HAL_VPU_EX_MVDInUsed(void)3380 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3381 {
3382 //MVD is in used for MVD or HVD_TSP mode.
3383 MS_U8 i;
3384 MS_U8 u8UseCnt = 0;
3385
3386 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3387 {
3388 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3389 #ifdef VDEC3
3390 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3391 #endif
3392 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3393 {
3394 u8UseCnt++;
3395 }
3396 }
3397
3398 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3399
3400 if (u8UseCnt != 0)
3401 {
3402 return TRUE;
3403 }
3404 else
3405 {
3406 return FALSE;
3407 }
3408 }
3409
HAL_VPU_EX_HVDInUsed(void)3410 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3411 {
3412 //HVD is in used for HVD or MVD in sub stream.
3413 MS_U8 i;
3414 MS_U8 u8UseCnt = 0;
3415 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3416 {
3417 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype))
3418 {
3419 u8UseCnt++;
3420 }
3421 }
3422
3423 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3424
3425 if (u8UseCnt != 0)
3426 {
3427 return TRUE;
3428 }
3429 else
3430 {
3431 return FALSE;
3432 }
3433 }
3434
HAL_VPU_EX_Mutex_Lock(void)3435 void HAL_VPU_EX_Mutex_Lock(void)
3436 {
3437 _HAL_VPU_Entry();
3438 }
3439
HAL_VPU_EX_Mutex_UnLock(void)3440 void HAL_VPU_EX_Mutex_UnLock(void)
3441 {
3442 _HAL_VPU_Release();
3443 }
3444
3445 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3446 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3447 {
3448 MS_U8 i;
3449 MS_U8 u8UseCnt = 0;
3450
3451 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3452 {
3453 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3454 {
3455 u8UseCnt++;
3456 }
3457 }
3458
3459 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3460
3461 if (u8UseCnt != 0)
3462 {
3463 return TRUE;
3464 }
3465 else
3466 {
3467 return FALSE;
3468 }
3469 }
3470
3471 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3472 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3473 {
3474 MS_U8 i;
3475 MS_U8 u8UseCnt = 0;
3476
3477 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3478 {
3479 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3480 {
3481 u8UseCnt++;
3482 }
3483 }
3484
3485 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3486
3487 if (u8UseCnt != 0)
3488 {
3489 return TRUE;
3490 }
3491 else
3492 {
3493 return FALSE;
3494 }
3495 }
3496 #endif
3497 #endif
3498
3499 //-----------------------------------------------------------------------------
3500 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3501 /// @brief \b Function \b Description: Set debug level
3502 /// @param -elevel \b IN : debug level
3503 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3504 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3505 {
3506 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3507
3508 switch (eLevel)
3509 {
3510 case E_VPU_EX_UART_LEVEL_ERR:
3511 {
3512 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3513 break;
3514 }
3515 case E_VPU_EX_UART_LEVEL_INFO:
3516 {
3517 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3518 break;
3519 }
3520 case E_VPU_EX_UART_LEVEL_DBG:
3521 {
3522 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3523 break;
3524 }
3525 case E_VPU_EX_UART_LEVEL_TRACE:
3526 {
3527 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3528 break;
3529 }
3530 case E_VPU_EX_UART_LEVEL_FW:
3531 {
3532 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3533 break;
3534 }
3535 default:
3536 {
3537 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3538 break;
3539 }
3540 }
3541 }
3542
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3543 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3544 {
3545 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3546 MS_U32 u32CmdArg = (MS_U32)eVerType;
3547 MS_U32 u32Version = 0xFFFFFFFF;
3548 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3549 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3550 {
3551 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3552 return u32Version;
3553 }
3554
3555 MS_BOOL bRet = false;
3556 MS_U32 u32TimeOut = 0xFFFFFFFF;
3557
3558 while(--u32TimeOut)
3559 {
3560 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3561 {
3562 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3563 if (false == bRet)
3564 {
3565 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3566 return u32Version;
3567 }
3568
3569 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3570 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3571 return u32Version;
3572 }
3573 }
3574
3575 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3576
3577 return u32Version;
3578 }
3579
HAL_VPU_EX_NotSupportDS(void)3580 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3581 {
3582 return TRUE;// maserati disable SN DS
3583 }
3584
3585 //-----------------------------------------------------------------------------
3586 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3587 /// @brief \b Function \b Description: Get VPU MIU base address
3588 /// @return - vpu MIU1 base
3589 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3590 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3591 {
3592 return VPU_MIU1BASE_ADDR;
3593 }
3594
3595
HAL_VPU_EX_GetSHMAddr(void)3596 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3597 {
3598 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
3599 {
3600 return 0;
3601 }
3602 return pVPUHalContext->u32VPUSHMAddr;
3603 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3604 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3605 {
3606 pVPUHalContext->bEnableVPUSecureMode = enable;
3607 return TRUE;
3608 }
3609
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3610 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3611 {
3612 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3613
3614 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3615 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3616 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3617 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3618 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3619 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3620 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3621 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3622
3623 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3624 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3625 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3626 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3627 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3628 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3629 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3630 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3631 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3632 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3633
3634 return TRUE;
3635 }
3636
3637 //-----------------------------------------------------------------------------
3638 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3639 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3640 /// @return - success/fail
3641 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3642 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3643 {
3644 #define MAX_CAPABILITY_INFO_NUM 8
3645 #define MAX_CODEC_TYPE_NUM 18
3646
3647 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3648 {
3649 //width, height , frmrate, profile, level, version bit rate reserved2
3650 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3651 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3652 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3653 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3654 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3655 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3656 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3657 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3658 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3659 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3660 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3661 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3662 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3663 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3664 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3665 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3666 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 160, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3667 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 160, 0},//E_HVD_EX_CODEC_TYPE_VP9
3668 };
3669
3670 if(eCodecType < MAX_CODEC_TYPE_NUM)
3671 {
3672 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3673 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3674 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3675 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3676 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3677 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3678 return TRUE;
3679 }
3680 else
3681 {
3682 return FALSE;
3683 }
3684 }
3685
3686 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3687 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3688 {
3689 (void) u32Id;
3690 BBU_STATE *bbu_state;
3691
3692 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3693 || (eDecType == E_VPU_EX_DECODER_VP8)
3694 #if SUPPORT_G2VP9
3695 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3696 #endif
3697 )
3698 {
3699 // MVD should not call this function.
3700 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3701 return;
3702 }
3703
3704 switch (eDecType)
3705 {
3706 case E_VPU_EX_DECODER_EVD:
3707 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3708 break;
3709 case E_VPU_EX_DECODER_HVD:
3710 case E_VPU_EX_DECODER_RVD:
3711 case E_VPU_EX_DECODER_MVC:
3712 default:
3713 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3714 break;
3715 }
3716
3717 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3718 return;
3719 }
3720
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3721 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3722 {
3723 (void) u32Id;
3724 BBU_STATE *bbu_state;
3725
3726 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3727 || (eDecType == E_VPU_EX_DECODER_VP8)
3728 #if SUPPORT_G2VP9
3729 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3730 #endif
3731 )
3732 {
3733 // MVD should not call this function.
3734 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3735 return TRUE;
3736 }
3737
3738 switch (eDecType)
3739 {
3740 case E_VPU_EX_DECODER_EVD:
3741 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3742 break;
3743 case E_VPU_EX_DECODER_HVD:
3744 case E_VPU_EX_DECODER_RVD:
3745 case E_VPU_EX_DECODER_MVC:
3746 default:
3747 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3748 break;
3749 }
3750
3751 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3752 }
3753
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3754 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3755 {
3756 (void) u32Id;
3757 BBU_STATE *bbu_state;
3758
3759 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3760 || (eDecType == E_VPU_EX_DECODER_VP8)
3761 #if SUPPORT_G2VP9
3762 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3763 #endif
3764 )
3765 {
3766 // MVD should not call this function.
3767 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3768 return;
3769 }
3770
3771 switch (eDecType)
3772 {
3773 case E_VPU_EX_DECODER_EVD:
3774 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3775 break;
3776 case E_VPU_EX_DECODER_HVD:
3777 case E_VPU_EX_DECODER_RVD:
3778 case E_VPU_EX_DECODER_MVC:
3779 default:
3780 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3781 break;
3782 }
3783
3784 if (bbu_state[u32BBUId].u32Used == 0)
3785 {
3786 bbu_state[u32BBUId].u8RegSetting = 0;
3787 }
3788
3789 return;
3790 }
3791
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3792 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3793 {
3794 MS_U32 i, max_bbu_cnt;
3795 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3796
3797 if(pTaskInfo == NULL)
3798 return retBBUId;
3799
3800 BBU_STATE *bbu_state;
3801 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3802 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3803
3804 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3805
3806 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3807
3808 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3809 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3810 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3811
3812 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3813 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3814
3815 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3816 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3817 */
3818 #if 1
3819 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3820 {
3821 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3822 if (bTSP)
3823 {
3824 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3825 {
3826 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3827 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3828 slq_state[u8TaskId].bTSP = TRUE;
3829 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3830 return u8TaskId;
3831 }
3832 }
3833 else
3834 {
3835 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3836 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3837 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3838 {
3839 if (slq_state[i].u32Used != 0)
3840 {
3841 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3842 {
3843 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3844 }
3845 }
3846 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3847 {
3848 avaliable_bbu_idx = i; // recored the first empty bbu
3849 }
3850 }
3851
3852 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3853
3854 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3855 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3856 slq_state[shared_bbu_idx].bTSP = FALSE;
3857 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3858 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3859 return shared_bbu_idx;
3860 }
3861 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3862 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3863 slq_state[u8TaskId].bTSP = FALSE;
3864 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3865
3866 if (bShareBBU == FALSE)
3867 {
3868 slq_state[u8TaskId].bTSP = TRUE;
3869 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3870 }
3871 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3872 return u8TaskId;
3873 }
3874 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3875 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3876 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3877 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3878
3879 if (bShareBBU == FALSE)
3880 {
3881 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3882 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3883 }
3884 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3885 return avaliable_bbu_idx;
3886 }
3887 else {
3888 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3889 }
3890 }
3891 }
3892 #if SUPPORT_G2VP9
3893 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3894 {
3895 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3896 // Don't care the return value, G2_VP9 will not use it.
3897 return 0;
3898 }
3899 #endif
3900 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3901 {
3902 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3903 // Don't care the return value, VP8 will not use it.
3904 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3905 return u8Offset;
3906 //return 0;
3907 }
3908 else
3909 {
3910 switch (pTaskInfo->eDecType)
3911 {
3912 case E_VPU_EX_DECODER_EVD:
3913 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3914 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3915 break;
3916 case E_VPU_EX_DECODER_HVD:
3917 case E_VPU_EX_DECODER_RVD:
3918 case E_VPU_EX_DECODER_MVC:
3919 default:
3920 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3921 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3922 break;
3923 }
3924
3925 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3926 if (bTSP)
3927 {
3928 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3929 {
3930 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3931 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3932 bbu_state[u8TaskId].bTSP = TRUE;
3933 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3934 slq_state[u8TaskId].bTSP = TRUE;
3935 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3936 return u8TaskId;
3937 }
3938 }
3939 else
3940 {
3941 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3942 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3943 for (i = 0; i < max_bbu_cnt; i++)
3944 {
3945 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3946 {
3947 if (bbu_state[i].bTSP == FALSE)
3948 {
3949 shared_bbu_idx = i;
3950 }
3951 }
3952 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3953 {
3954 avaliable_bbu_idx = i;
3955 }
3956 }
3957
3958 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3959
3960 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3961 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3962 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3963 return shared_bbu_idx;
3964 }
3965 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3966 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3967
3968 if (bShareBBU == FALSE)
3969 {
3970 bbu_state[u8TaskId].bTSP = TRUE;
3971 VPRINTF("[NDec] occupy one BBU_ID \n");
3972 }
3973 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3974 return u8TaskId;
3975 }
3976 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3977 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3978
3979 if (bShareBBU == FALSE)
3980 {
3981 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3982 VPRINTF("[NDec] occupy one BBU_ID \n");
3983 }
3984 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3985 return avaliable_bbu_idx;
3986 }
3987 else {
3988 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3989 }
3990 }
3991 }
3992 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3993 MS_U32 j;
3994 MS_BOOL Got = FALSE;
3995 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3996 {
3997 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3998 {
3999 if(slq_state[i].u32Used != 0)
4000 {
4001 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
4002 {
4003 retBBUId = i;
4004 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4005 slq_state[retBBUId].bTSP = bTSP;
4006 slq_state[retBBUId].bUsedbyMVD = TRUE;
4007 return retBBUId;
4008 }
4009 }
4010 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
4011 {
4012 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
4013 {
4014 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
4015 {
4016 Got = TRUE;
4017 retBBUId = i;
4018 }
4019 }
4020
4021 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
4022 {
4023 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
4024 {
4025 Got = TRUE;
4026 retBBUId = i;
4027 }
4028 }
4029
4030 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
4031 retBBUId = i;
4032 }
4033 }
4034 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4035 {
4036 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4037 slq_state[retBBUId].bTSP = bTSP;
4038 slq_state[retBBUId].bUsedbyMVD = TRUE;
4039 }
4040 }
4041 #if SUPPORT_G2VP9
4042 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4043 {
4044 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4045 // Don't care the return value, G2_VP9 will not use it.
4046 return 0;
4047 }
4048 #endif
4049 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4050 {
4051 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4052 // Don't care the return value, VP8 will not use it.
4053 return 0;
4054 }
4055 else // HVD/EVD case
4056 {
4057 switch (pTaskInfo->eDecType)
4058 {
4059 case E_VPU_EX_DECODER_EVD:
4060 case E_VPU_EX_DECODER_G2VP9:
4061 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4062 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4063 break;
4064 case E_VPU_EX_DECODER_HVD:
4065 case E_VPU_EX_DECODER_RVD:
4066 case E_VPU_EX_DECODER_MVC:
4067 default:
4068 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4069 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4070 break;
4071 }
4072
4073 for (i = 0; i < max_bbu_cnt; i++)
4074 {
4075 if(bbu_state[i].u32Used != 0)
4076 {
4077 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
4078 {
4079 retBBUId = i;
4080 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4081 bbu_state[retBBUId].bTSP = bTSP;
4082 return retBBUId;
4083 }
4084 }
4085 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
4086 {
4087 if(i < MAX_MVD_SLQ_COUNT)
4088 {
4089 if(!bTSP) //HVD/EVD first MM case
4090 {
4091 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
4092 {
4093 retBBUId = i;
4094 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4095 bbu_state[retBBUId].bTSP = bTSP;
4096 return retBBUId;
4097 }
4098
4099 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
4100 retBBUId = i;
4101 }
4102 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
4103 {
4104 retBBUId = i;
4105 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4106 bbu_state[retBBUId].bTSP = bTSP;
4107 slq_state[retBBUId].bUsedbyMVD = FALSE;
4108 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4109 slq_state[retBBUId].bTSP = bTSP;
4110 return retBBUId;
4111 }
4112 }
4113 }
4114 }
4115 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4116 {
4117 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4118 bbu_state[retBBUId].bTSP = bTSP;
4119 if(bTSP)
4120 {
4121 slq_state[retBBUId].bUsedbyMVD = FALSE;
4122 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4123 slq_state[retBBUId].bTSP = bTSP;
4124 }
4125 }
4126 }
4127 #endif
4128 return retBBUId;
4129 }
4130
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)4131 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
4132 {
4133 MS_U32 max_bbu_cnt;
4134 BBU_STATE *bbu_state;
4135 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
4136
4137 if(pTaskInfo == NULL)
4138 return FALSE;
4139 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4140 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4141
4142 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4143 /* MS_U32 i;
4144 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4145 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4146
4147 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4148 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
4149
4150 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4151 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
4152 */
4153 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4154 {
4155 // TO DO
4156 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4157 {
4158 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4159 slq_state[u32BBUId].bTSP = FALSE;
4160 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4161 return TRUE;
4162 }
4163 }
4164 #if SUPPORT_G2VP9
4165 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4166 {
4167 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4168 return TRUE;
4169 }
4170 #endif
4171 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4172 {
4173 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4174 return TRUE;
4175 }
4176 else
4177 {
4178 switch (pTaskInfo->eDecType)
4179 {
4180 case E_VPU_EX_DECODER_EVD:
4181 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4182 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4183 break;
4184 case E_VPU_EX_DECODER_HVD:
4185 case E_VPU_EX_DECODER_RVD:
4186 case E_VPU_EX_DECODER_MVC:
4187 default:
4188 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4189 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4190 break;
4191 }
4192
4193 if (u32BBUId < max_bbu_cnt)
4194 {
4195 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4196 bbu_state[u32BBUId].bTSP = FALSE;
4197
4198 if (bTSP)
4199 {
4200 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4201 slq_state[u32BBUId].bTSP = FALSE;
4202 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4203 }
4204
4205 #if 1
4206 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4207 #else
4208 if (bbu_state[u32BBUId].u32Used == 0)
4209 {
4210 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4211 }
4212 #endif
4213
4214 return TRUE;
4215 }
4216 }
4217 return FALSE;
4218 }
4219
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4220 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4221 {
4222 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4223
4224 if (CHECK_NULL_PTR(pstVBBU))
4225 return 0;
4226 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4227 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4228 MS_U32 u32Vacancy = 0;
4229
4230 if (u32WrPtr == u32RdPtr)
4231 {
4232 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4233 }
4234 else if (u32WrPtr > u32RdPtr)
4235 {
4236 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4237 }
4238 else
4239 {
4240 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4241 }
4242
4243 return u32Vacancy;
4244 }
4245
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4246 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4247 {
4248 return MAX_VDEC_VBBU_ENTRY_COUNT;
4249 }
4250
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4251 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4252 {
4253 return pVPUHalContext->u32FWCodeAddr;
4254 }
4255
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4256 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4257 {
4258 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4259 #if SUPPORT_G2VP9
4260 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4261 #endif
4262
4263 if (CHECK_NULL_PTR(pstVBBU))
4264 return FALSE;
4265 MsOS_ReadMemory();
4266 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4267
4268 if(NULL == stEntry)
4269 {
4270 return 0;
4271 }
4272
4273 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4274 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4275 {
4276 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4277 }
4278 else
4279 {
4280 #if SUPPORT_G2VP9
4281 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4282 {
4283 if (stEntry->u32Offset == 0)
4284 return 0;
4285 else
4286 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4287 }
4288 else
4289 #endif
4290 {
4291 return stEntry->u32Offset;
4292 }
4293 }
4294 }
4295
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4296 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4297 {
4298 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4299 VDEC_VBBU_Entry *stEntry;
4300 #if SUPPORT_G2VP9
4301 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4302 #endif
4303
4304 MsOS_ReadMemory();
4305 if (CHECK_NULL_PTR(pstVBBU))
4306 return 0;
4307 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4308
4309 if (u32WrPtr == 0)
4310 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4311 else
4312 u32WrPtr--;
4313
4314 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4315
4316 if(NULL == stEntry)
4317 {
4318 return 0;
4319 }
4320
4321 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4322 #if SUPPORT_G2VP9
4323 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4324 {
4325 if (stEntry->u32Offset == 0)
4326 return 0;
4327 else
4328 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4329 }
4330 else
4331 #endif
4332 {
4333 return stEntry->u32Offset + stEntry->u32Length;
4334 }
4335 }
4336
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4337 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4338 {
4339 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4340 #if SUPPORT_G2VP9
4341 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4342 #endif
4343
4344 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4345 return FALSE;
4346 MsOS_ReadMemory();
4347 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4348 MS_U32 u32NewWrPtr;
4349
4350 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4351 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4352 {
4353 u32NewWrPtr = 0;
4354 }
4355
4356 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4357
4358 stEntry->u32Offset = stVpuPkt->u32Offset;
4359
4360 #if SUPPORT_G2VP9
4361 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4362 {
4363 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4364 }
4365 #endif
4366
4367 stEntry->u32Length = stVpuPkt->u32Length;
4368 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4369 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4370 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4371 stEntry->u8Version = stVpuPkt->u8Version;
4372
4373 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4374
4375 pstVBBU->u32WrPtr = u32NewWrPtr;
4376
4377 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4378
4379 MsOS_FlushMemory();
4380
4381 return TRUE;
4382 }
4383
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4384 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4385 {
4386 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4387
4388 if (CHECK_NULL_PTR(pstVBBU))
4389 return FALSE;
4390 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4391 }
4392
4393 ///-----------------------------------------------------------------------------
4394 /// specify the command send to Mail box or DRAM
4395 /// @return TRUE or FALSE
4396 /// - TRUE, Mail box
4397 /// - FALSE, Dram
4398 /// @param u32Cmd \b IN: Command is going to be sned
4399 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4400 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4401 {
4402 MS_BOOL bResult = TRUE;
4403
4404 switch (u32Cmd)
4405 {
4406 // *********** Runtime action Command
4407 /* case E_HVD_CMD_RELEASE_DISPQ:
4408 case E_HVD_CMD_UPDATE_DISPQ:
4409 case E_HVD_CMD_FLUSH_DEC_Q:
4410 case E_HVD_CMD_FLUSH:
4411 case E_HVD_CMD_PLAY:
4412 case E_HVD_CMD_PAUSE:
4413 case E_HVD_CMD_STOP:
4414 case E_HVD_CMD_STEP_DECODE:
4415 case E_HVD_CMD_SKIP_DEC:
4416 case E_HVD_CMD_DISP_I_DIRECT:*/
4417 // *********** Dual-Stream Create Task Command
4418 case E_DUAL_CMD_TASK0_HVD_BBU:
4419 case E_DUAL_CMD_TASK0_HVD_TSP:
4420 case E_DUAL_CMD_TASK0_MVD_SLQ:
4421 case E_DUAL_CMD_TASK0_MVD_TSP:
4422 case E_DUAL_CMD_TASK1_HVD_BBU:
4423 case E_DUAL_CMD_TASK1_HVD_TSP:
4424 case E_DUAL_CMD_MODE:
4425 #ifndef _WIN32
4426 case E_DUAL_CMD_TASK1_MVD_SLQ:
4427 case E_DUAL_CMD_TASK1_MVD_TSP:
4428 #endif
4429 case E_DUAL_CMD_DEL_TASK:
4430 case E_DUAL_CMD_SINGLE_TASK:
4431 case E_DUAL_VERSION:
4432 case E_DUAL_R2_CMD_EXIT:
4433 case E_DUAL_CMD_STC_MODE:
4434 #ifdef VDEC3
4435 case E_DUAL_R2_CMD_FBADDR:
4436 case E_DUAL_R2_CMD_FBSIZE:
4437 // *********** N-Streams
4438 case E_NST_CMD_TASK_HVD_TSP:
4439 case E_NST_CMD_TASK_HVD_BBU:
4440 case E_NST_CMD_TASK_MVD_TSP:
4441 case E_NST_CMD_TASK_MVD_SLQ:
4442 case E_NST_CMD_DEL_TASK:
4443 case E_NST_CMD_COMMON_MASK:
4444 case E_NST_CMD_COMMON_CMD1:
4445 #endif
4446 case E_DUAL_CMD_COMMON:
4447 {
4448 bResult = TRUE;
4449 }
4450 break;
4451 default:
4452 {
4453 bResult = FALSE;
4454 }
4455 break;
4456 }
4457
4458 return bResult;
4459 }
4460
4461 ///-----------------------------------------------------------------------------
4462 /// specify the command send to Mail box or DRAM
4463 /// @return TRUE or FALSE
4464 /// - TRUE, Mail box
4465 /// - FALSE, Dram
4466 /// @param u32Cmd \b IN: Command is going to be sned
4467 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4468 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4469 {
4470 MS_BOOL bResult = TRUE;
4471
4472 switch (u32Cmd)
4473 {
4474 // *********** Runtime action Command
4475 case E_HVD_CMD_RELEASE_DISPQ:
4476 case E_HVD_CMD_UPDATE_DISPQ:
4477 case E_HVD_CMD_FLUSH_DEC_Q:
4478 case E_HVD_CMD_PAUSE:
4479 case E_HVD_CMD_FLUSH:
4480 case E_HVD_CMD_PLAY:
4481 case E_HVD_CMD_STOP:
4482 case E_HVD_CMD_SKIP_DEC:
4483 case E_HVD_CMD_DISP_I_DIRECT:
4484 case E_HVD_CMD_STEP_DECODE:
4485 case E_HVD_CMD_INC_DISPQ_NUM:
4486 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4487 {
4488 bResult = TRUE;
4489 }
4490 break;
4491 default:
4492 {
4493 bResult = FALSE;
4494 }
4495 break;
4496 }
4497
4498 return bResult;
4499 }
4500
4501 ///-----------------------------------------------------------------------------
4502 /// Send message to HVD stream command queue
4503 /// @return TRUE or FALSE
4504 /// - TRUE, Success
4505 /// - FALSE, Failed
4506 /// @param u32DramAddr \b IN: address to be writen
4507 /// @param u32Msg \b IN: data to be writen
4508 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4509 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4510 {
4511 MS_BOOL bResult = TRUE;
4512
4513 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4514
4515 WRITE_LONG(u32DramAddr,u32Msg);
4516
4517 return bResult;
4518 }
4519
4520 ///-----------------------------------------------------------------------------
4521 /// Read task share memory to specify that task command queue is empty or not
4522 /// @return TRUE or FALSE
4523 /// - TRUE, Empty
4524 /// - FALSE, Non empty
4525 /// @param u32Id \b IN: Task information
4526 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4527 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4528 {
4529 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4530 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4531 if (!cmd_q)
4532 {
4533 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4534 return FALSE;
4535 }
4536
4537 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4538 }
4539
4540 ///-----------------------------------------------------------------------------
4541 /// Read task share memory to specify that task command queue is full or not
4542 /// @return TRUE or FALSE
4543 /// - TRUE, Full
4544 /// - FALSE, Non full
4545 /// @param u32Id \b IN: Task information
4546 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4547 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4548 {
4549 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4550 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4551 if (!cmd_q)
4552 {
4553 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4554 return TRUE;
4555 }
4556 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4557
4558 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4559 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4560
4561 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4562 }
4563
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4564 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4565 {
4566 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4567 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4568 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4569
4570 #if HVD_ENABLE_MVC
4571 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4572 {
4573 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4574 }
4575 #endif
4576
4577 if (CHECK_NULL_PTR(cmd_q))
4578 {
4579 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4580 return bResult;
4581 }
4582 MS_VIRT u32CmdQWdPtr;
4583
4584 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4585 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4586
4587 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4588 return E_HVD_COMMAND_QUEUE_FULL;
4589 else
4590 {
4591 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4592 }
4593
4594 switch (u8CmdType)
4595 {
4596 case E_HVD_CMDQ_CMD:
4597 {
4598 u32Msg |= (u8TaskID << 24);
4599 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4600
4601 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4602
4603 if (bResult)
4604 {
4605 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4606
4607 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4608 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4609
4610 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4611 }
4612 break;
4613 }
4614 case E_HVD_CMDQ_ARG:
4615 {
4616 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4617 if (bResult)
4618 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4619 break;
4620 }
4621 default:
4622 {
4623 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4624 break;
4625 }
4626 }
4627
4628 MsOS_FlushMemory();
4629
4630 return bResult;
4631 }
4632
4633 ///-----------------------------------------------------------------------------
4634 /// Read task share memory to specify that task display command queue is empty or not
4635 /// @return TRUE or FALSE
4636 /// - TRUE, Empty
4637 /// - FALSE, Non empty
4638 /// @param u32Id \b IN: Task information
4639 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4640 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4641 {
4642 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4643 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4644 if (!cmd_q)
4645 {
4646 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4647 return FALSE;
4648 }
4649
4650 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4651 }
4652
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4653 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4654 {
4655 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4656 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4657 if (!cmd_q)
4658 {
4659 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4660 return TRUE;
4661 }
4662
4663 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4664
4665 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4666 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4667
4668 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4669 }
4670
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4671 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4672 {
4673 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4674 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4675 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4676
4677 #if HVD_ENABLE_MVC
4678 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4679 {
4680 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4681 }
4682 #endif
4683
4684 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4685 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4686
4687 if (CHECK_NULL_PTR(cmd_q))
4688 {
4689 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4690 return bResult;
4691 }
4692
4693 MS_VIRT u32DISPCMDQWdPtr;
4694
4695 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4696 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4697
4698 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4699 return E_HVD_COMMAND_QUEUE_FULL;
4700 else
4701 {
4702 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4703 }
4704
4705 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4706
4707 switch (u8CmdType)
4708 {
4709 case E_HVD_CMDQ_CMD:
4710 {
4711 u32Msg |= (u8TaskID << 24);
4712 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4713
4714 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4715
4716 if (bResult)
4717 {
4718 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4719
4720 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4721 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4722
4723 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4724 }
4725 break;
4726 }
4727 case E_HVD_CMDQ_ARG:
4728 {
4729 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4730 if (bResult)
4731 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4732 break;
4733 }
4734 default:
4735 {
4736 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4737 break;
4738 }
4739 }
4740
4741 MsOS_FlushMemory();
4742
4743 return bResult;
4744 }
4745
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4746 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4747 {
4748 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4749 MS_U32 u32StAddr;
4750 MS_U8 u8TmpMiuSel;
4751
4752 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4753
4754 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4755
4756 return TRUE;
4757 }
4758 #endif
4759
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4760 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4761 {
4762 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4763
4764 if(u32address >= HAL_MIU1_BASE)
4765 {
4766 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4767 }
4768 else
4769 {
4770 pVPUHalContext->u32DynamicFBAddress = u32address;
4771 }
4772
4773 pVPUHalContext->u32DynamicFBSize = u32Size;
4774 }
4775 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4776 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4777 {
4778 MS_S32 handle;
4779 switch(eClkPortType)
4780 {
4781 case E_VPU_EX_CLKPORT_MVD:
4782 {
4783 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4784 if(bEnable)
4785 {
4786 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4787 }
4788 else
4789 {
4790 Drv_Clkm_Clk_Gate_Disable(handle);
4791 }
4792 break;
4793 }
4794 case E_VPU_EX_CLKPORT_MVD_CORE:
4795 {
4796 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4797 if(bEnable)
4798 {
4799 Drv_Clkm_Set_Clk_Source(handle, "");
4800 }
4801 else
4802 {
4803 Drv_Clkm_Clk_Gate_Disable(handle);
4804 }
4805 break;
4806 }
4807 case E_VPU_EX_CLKPORT_MVD_PAS:
4808 {
4809 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4810 if(bEnable)
4811 {
4812 Drv_Clkm_Set_Clk_Source(handle, "");
4813 }
4814 else
4815 {
4816 Drv_Clkm_Clk_Gate_Disable(handle);
4817 }
4818 break;
4819 }
4820 case E_VPU_EX_CLKPORT_HVD:
4821 {
4822 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4823 if(bEnable)
4824 {
4825 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4826 }
4827 else
4828 {
4829 Drv_Clkm_Clk_Gate_Disable(handle);
4830 }
4831 break;
4832 }
4833 case E_VPU_EX_CLKPORT_HVD_IDB:
4834 {
4835 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4836 if(bEnable)
4837 {
4838 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4839 }
4840 else
4841 {
4842 Drv_Clkm_Clk_Gate_Disable(handle);
4843 }
4844 break;
4845 }
4846 case E_VPU_EX_CLKPORT_HVD_AEC:
4847 {
4848 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4849 if(bEnable)
4850 {
4851 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4852 }
4853 else
4854 {
4855 Drv_Clkm_Clk_Gate_Disable(handle);
4856 }
4857 break;
4858 }
4859 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4860 {
4861 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4862 if(bEnable)
4863 {
4864 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4865 }
4866 else
4867 {
4868 Drv_Clkm_Clk_Gate_Disable(handle);
4869 }
4870 break;
4871 }
4872 case E_VPU_EX_CLKPORT_VP8:
4873 {
4874 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4875 if(bEnable)
4876 {
4877 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4878 }
4879 else
4880 {
4881 Drv_Clkm_Clk_Gate_Disable(handle);
4882 }
4883 break;
4884 }
4885 case E_VPU_EX_CLKPORT_EVD:
4886 {
4887 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4888 if(bEnable)
4889 {
4890 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4891 }
4892 else
4893 {
4894 Drv_Clkm_Clk_Gate_Disable(handle);
4895 }
4896 break;
4897 }
4898 case E_VPU_EX_CLKPORT_EVD_PPU:
4899 {
4900 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4901 if(bEnable)
4902 {
4903 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4904 }
4905 else
4906 {
4907 Drv_Clkm_Clk_Gate_Disable(handle);
4908 }
4909 break;
4910 }
4911 case E_VPU_EX_CLKPORT_EVD_LITE:
4912 {
4913 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4914 if(bEnable)
4915 {
4916 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4917 }
4918 else
4919 {
4920 Drv_Clkm_Clk_Gate_Disable(handle);
4921 }
4922 break;
4923 }
4924 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4925 {
4926 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4927 if(bEnable)
4928 {
4929 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4930 }
4931 else
4932 {
4933 Drv_Clkm_Clk_Gate_Disable(handle);
4934 }
4935 break;
4936 }
4937 case E_VPU_EX_CLKPORT_VD_MHEG5:
4938 {
4939 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4940 if(bEnable)
4941 {
4942 Drv_Clkm_Set_Clk_Source(handle, "");
4943 }
4944 else
4945 {
4946 Drv_Clkm_Clk_Gate_Disable(handle);
4947 }
4948 break;
4949 }
4950 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4951 {
4952 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4953 if(bEnable)
4954 {
4955 Drv_Clkm_Set_Clk_Source(handle, "");
4956 }
4957 else
4958 {
4959 Drv_Clkm_Clk_Gate_Disable(handle);
4960 }
4961 break;
4962 }
4963 }
4964 }
4965 #endif //#ifdef CONFIG_MSTAR_CLKM
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4966 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4967 {
4968 MS_SIZE FrameBufferSize = 0;
4969
4970 switch(eCodecType)
4971 {
4972 case E_VPU_EX_CODEC_TYPE_MPEG2:
4973 case E_VPU_EX_CODEC_TYPE_H263:
4974 case E_VPU_EX_CODEC_TYPE_MPEG4:
4975 case E_VPU_EX_CODEC_TYPE_DIVX311:
4976 case E_VPU_EX_CODEC_TYPE_DIVX412:
4977 case E_VPU_EX_CODEC_TYPE_FLV:
4978 FrameBufferSize = 0x1E00000;
4979 break;
4980 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4981 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4982 FrameBufferSize = 0x6C00000;
4983 break;
4984 case E_VPU_EX_CODEC_TYPE_RV8:
4985 case E_VPU_EX_CODEC_TYPE_RV9:
4986 FrameBufferSize = 0x1B00000;
4987 break;
4988 case E_VPU_EX_CODEC_TYPE_VP8:
4989 FrameBufferSize = 0x1500000;
4990 break;
4991 case E_VPU_EX_CODEC_TYPE_H264:
4992 FrameBufferSize = 0x8200000;
4993 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4994 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4995 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4996 break;
4997 case E_VPU_EX_CODEC_TYPE_AVS:
4998 #if VPU_FIELD_DETECTOR
4999 FrameBufferSize = 0x3600000;
5000 #else
5001 FrameBufferSize = 0x1B00000;
5002 #endif
5003 break;
5004 case E_VPU_EX_CODEC_TYPE_MJPEG:
5005 FrameBufferSize = 0x2800000;
5006 break;
5007 case E_VPU_EX_CODEC_TYPE_MVC:
5008 FrameBufferSize = 0x4200000;
5009 break;
5010 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
5011 FrameBufferSize = 0xB000000;
5012 break;
5013 case E_VPU_EX_CODEC_TYPE_HEVC:
5014 #if SUPPORT_MSVP9
5015 case E_VPU_EX_CODEC_TYPE_VP9:
5016 #endif
5017 FrameBufferSize = 0xA000000;
5018 break;
5019 #if !SUPPORT_MSVP9
5020 case E_VPU_EX_CODEC_TYPE_VP9:
5021 FrameBufferSize = 0x7800000;
5022 break;
5023 #endif
5024 default:
5025 FrameBufferSize = 0;
5026 break;
5027 }
5028
5029 return FrameBufferSize;
5030 }
5031
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)5032 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
5033 {
5034 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5035 }
5036
5037 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)5038 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
5039 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
5040 {
5041 MS_SIZE FrameBufferSize = 0;
5042
5043 if (!offset || !length)
5044 return FALSE;
5045
5046 total_length -= unUseSize;
5047 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
5048 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
5049
5050 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5051
5052 if(FrameBufferSize == 0)
5053 {
5054 return FALSE;
5055 }
5056 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
5057 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
5058 if (total_length < FrameBufferSize)
5059 {
5060 *offset = unUseSize;
5061 *length = total_length;
5062 }
5063 else // todo, dual decode case
5064 {
5065 *offset = unUseSize;
5066 *length = FrameBufferSize;
5067 }
5068 return TRUE;
5069 }
5070
HAL_VPU_EX_strcmp(const char * string1,const char * string2)5071 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
5072 {
5073 int iRet, i;
5074
5075 i = 0;
5076 while(string1[i] || string2[i])
5077 {
5078 iRet = string1[i] - string2[i];
5079 if(iRet)
5080 {
5081 return iRet;
5082 }
5083 i++;
5084 }
5085 return 0;
5086 }
5087
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)5088 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
5089 {
5090 typedef enum
5091 {
5092 E_CAP_NDEC_FB_MIU_SELECT,
5093 E_CAP_NDEC_NSTREAM_FB_SIZE,
5094 E_CAP_NDEC_NSTREAM_BS_SIZE,
5095 E_CAP_NDEC_SUPPORT_SHAREBBU,
5096 E_CAP_SUPPORT_ALLOCATOR,
5097
5098 } VPU_EX_GetCapabilityCmdId;
5099
5100 typedef struct
5101 {
5102 VPU_EX_GetCapabilityCmdId eCmdId;
5103 MS_U8 u8CmdName[32];
5104
5105 } VPU_EX_GetCapabilityCmd;
5106
5107 static VPU_EX_GetCapabilityCmd stCapCmd[] =
5108 {
5109 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
5110 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
5111 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
5112 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
5113 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
5114 };
5115
5116 MS_U32 bRet = FALSE;
5117 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
5118 MS_U32 u32CmdCnt;
5119
5120 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
5121 {
5122 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
5123 {
5124 bRet = TRUE;
5125 switch(stCapCmd[u32CmdCnt].eCmdId)
5126 {
5127 case E_CAP_NDEC_FB_MIU_SELECT:
5128 {
5129 VPU_EX_CodecType eCodecType = *((VPU_EX_CodecType *)pParamIn);
5130 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5131 if((eCodecType == E_VPU_EX_CODEC_TYPE_HEVC) ||
5132 (eCodecType == E_VPU_EX_CODEC_TYPE_VP9) ||
5133 (eCodecType == E_VPU_EX_CODEC_TYPE_HEVC_DV))
5134 {
5135 *pSupport = TRUE;
5136 }
5137 else
5138 {
5139 *pSupport = FALSE;
5140 }
5141 }
5142 break;
5143
5144 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
5145 case E_CAP_NDEC_NSTREAM_FB_SIZE:
5146 {
5147 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5148 *pSize = 0x1300000; // 19M
5149 }
5150 break;
5151
5152 // FIXME: Patch for waiting dynamic bitstream buffer
5153 case E_CAP_NDEC_NSTREAM_BS_SIZE:
5154 {
5155 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5156 *pSize = 0x400000; // 4M
5157 }
5158 break;
5159
5160 case E_CAP_NDEC_SUPPORT_SHAREBBU:
5161 {
5162 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
5163 *pbSupportShareBBU = TRUE;
5164 }
5165 break;
5166
5167 case E_CAP_SUPPORT_ALLOCATOR:
5168 {
5169 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5170 *pSupport = TRUE;
5171 }
5172 break;
5173
5174 default:
5175 bRet = FALSE;
5176 break;
5177 }
5178 }
5179 }
5180
5181 return bRet;
5182 }
5183
5184 #else
5185 #include "halVPU_EX.h"
5186 #include "drvMMIO.h"
5187 #include "../../../../vdec_v2/hal/maserati/hvd_ex/regHVD_EX.h"
5188 #include "halCHIP.h"
5189
5190 #if defined(MSOS_TYPE_NUTTX)
5191 extern int lib_lowprintf(const char *fmt, ...);
5192 #define PRINTF lib_lowprintf
5193 #elif defined(MSOS_TYPE_OPTEE)
5194 #define PRINTF printf
5195 #endif
5196
5197 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5198 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5199
5200 MS_U8 u8FW_Binary[] = {
5201 #include "fwVPU.dat"
5202 };
5203
5204 MS_U32 u32HVDRegOSBase;
5205
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5206 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5207 {
5208 //PRINTF("do load code,u32DestAddr %x\n",addr);
5209 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5210 MAsm_CPU_Sync();
5211 MsOS_FlushMemory();
5212
5213 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5214 {
5215 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5216 return FALSE;
5217 }
5218 return TRUE;
5219 }
5220
HAL_VPU_EX_SetLockDownRegister(void * param)5221 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5222 {
5223 #if 1
5224 MS_PHY u32StAddr_main;
5225 MS_PHY u32StAddr_sub;
5226 MS_U32 u32NonPMBankSize = 0;
5227 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5228
5229 if(param == NULL)
5230 {
5231 return FALSE;
5232 }
5233
5234 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5235
5236 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5237
5238 // ES buffer
5239 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5240 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5241
5242
5243 MS_PHY u32StartOffset;
5244 MS_U8 u8MiuSel;
5245
5246 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5247 u32StAddr_main = u32StartOffset;
5248
5249 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5250 u32StAddr_sub = u32StartOffset;
5251
5252 //Lock down register
5253 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5254 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5255
5256 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
5257 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
5258 //~
5259
5260 // Lock Down
5261 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5262 //~
5263 #endif
5264 return TRUE;
5265 }
5266
5267 #endif
5268