1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101
102 #if defined(REDLION_LINUX_KERNEL_ENVI)
103 #include "drvHVD_Common.h"
104 #else
105 #include "MsCommon.h"
106 #endif
107
108 #include "MsOS.h"
109 #include "asmCPU.h"
110
111
112 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
113
114 // Internal Definition
115 #include "regVPU_EX.h"
116 #include "halVPU_EX.h"
117 #include "halCHIP.h"
118 #if defined(VDEC3)
119 #include "../../../drv/hvd_v3/drvHVD_def.h"
120 #include "../hvd_v3/fwHVD_if.h"
121 #include "../mvd_v3/mvd4_interface.h"
122 #include "halHVD_EX.h"
123 #else
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #endif
128 #include "../../../drv/hvd_v3/drvHVD_EX.h"
129 #include "controller.h"
130
131 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
132 #include "ms_decompress.h"
133 #include "ms_decompress_priv.h"
134 #endif
135 #include "../../drv/mbx/apiMBX_St.h"
136 #include "../../drv/mbx/apiMBX.h"
137
138 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
139 #include "drvSERFLASH.h"
140 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
141 #endif
142
143
144
145 #ifndef ANDROID
146 #define VPRINTF printf
147 #else
148 #include <sys/mman.h>
149 #include <cutils/ashmem.h>
150 #include <cutils/log.h>
151 #define VPRINTF ALOGD
152 #endif
153
154
155 //-------------------------------------------------------------------------------------------------
156 // Driver Compiler Options
157 //-------------------------------------------------------------------------------------------------
158
159
160 //-------------------------------------------------------------------------------------------------
161 // Local Defines
162 //-------------------------------------------------------------------------------------------------
163 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
164
165 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
166 #ifdef VDEC3
167 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
168 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
169 #define MAX_MVD_SLQ_COUNT 2
170 #define MAX_SUPPORT_DECODER_NUM 16
171 #else
172 #define MAX_SUPPORT_DECODER_NUM 2
173 #endif
174 typedef enum
175 {
176 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
177 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
178 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
179 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
180
181
182 typedef enum
183 {
184 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
185 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
186 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
187 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
188 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
189 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
190
191 typedef enum
192 {
193 E_VPU_UART_CTRL_DISABLE = BIT(4),
194 E_VPU_UART_CTRL_ERR = BIT(0),
195 E_VPU_UART_CTRL_INFO = BIT(1),
196 E_VPU_UART_CTRL_DBG = BIT(2),
197 E_VPU_UART_CTRL_FW = BIT(3),
198 E_VPU_UART_CTRL_MUST = BIT(4),
199 E_VPU_UART_CTRL_TRACE = BIT(5),
200 } VPU_EX_UartCtrl;
201
202 typedef struct
203 {
204 HAL_VPU_StreamId eStreamId;
205 VPU_EX_DecoderType eDecodertype;
206 } VPU_EX_Stream;
207
208
209 #define VPU_MSG_ERR(format, args...) \
210 do \
211 { \
212 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
213 { \
214 printf("[VPU][ERR]%s:", __FUNCTION__); \
215 printf(format, ##args); \
216 } \
217 } while (0)
218
219 #define VPU_MSG_DBG(format, args...) \
220 do \
221 { \
222 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
223 { \
224 printf("[VPU][DBG]%s:", __FUNCTION__); \
225 printf(format, ##args); \
226 } \
227 } while (0)
228
229 #define VPU_MSG_INFO(format, args...) \
230 do \
231 { \
232 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
233 { \
234 printf("[VPU][INF]%s:", __FUNCTION__); \
235 printf(format, ##args); \
236 } \
237 } while (0)
238
239 //------------------------------ MIU SETTINGS ----------------------------------
240 #ifdef EVDR2
241 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
242 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
243 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))
244
245 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
246 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
247 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
248
249 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
250 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
251 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
252
253
254 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
255 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
256 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
257 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
258 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
259 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
260 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
261 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
262 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))) //g08
263 #endif
264
265
266
267 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
268 do \
269 { \
270 if (miu_clients##_ON_MIU0 == 1) \
271 { \
272 _MaskMiuReq_##miu_clients(mask); \
273 } \
274 else \
275 { \
276 if (miu_clients##_ON_MIU1 == 1) \
277 { \
278 _MaskMiu1Req_##miu_clients(mask); \
279 } \
280 else if (miu_clients##_ON_MIU2 == 1) \
281 { \
282 _MaskMiu2Req_##miu_clients(mask); \
283 } \
284 } \
285 } while(0)
286
287
288
289
290 #if ENABLE_VPU_MUTEX_PROTECTION
291 static MS_S32 s32VPUMutexID = -1;
292 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
293
294 #define _HAL_VPU_MutexCreate() \
295 if (s32VPUMutexID < 0) \
296 { \
297 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
298 }
299
300 #define _HAL_VPU_MutexDelete() \
301 if (s32VPUMutexID >= 0) \
302 { \
303 MsOS_DeleteMutex(s32VPUMutexID); \
304 s32VPUMutexID = -1; \
305 }
306
307 #define _HAL_VPU_Entry() \
308 if (s32VPUMutexID >= 0) \
309 { \
310 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
311 { \
312 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
313 } \
314 }
315
316 #define _HAL_VPU_Return(_ret) \
317 { \
318 if (s32VPUMutexID >= 0) \
319 { \
320 MsOS_ReleaseMutex(s32VPUMutexID); \
321 } \
322 return _ret; \
323 }
324
325 #define _HAL_VPU_Release() \
326 { \
327 if (s32VPUMutexID >= 0) \
328 { \
329 MsOS_ReleaseMutex(s32VPUMutexID); \
330 } \
331 }
332 #else
333 #define _HAL_VPU_MutexCreate()
334 #define _HAL_VPU_MutexDelete()
335 #define _HAL_VPU_Entry()
336 #define _HAL_VPU_Return(_ret) {return _ret;}
337 #define _HAL_VPU_Release()
338 #endif
339
340 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
341 #define VPU_CMD_TIMEOUT 1000 // 1 sec
342
343 //-------------------------------------------------------------------------------------------------
344 // Local Structures
345 //-------------------------------------------------------------------------------------------------
346 typedef struct _VPU_HWInitFunc
347 {
348 MS_BOOL (*pfMVDHW_Init)(void);
349 MS_BOOL (*pfMVDHW_Deinit)(void);
350 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
351 MS_BOOL (*pfHVDHW_Deinit)(void);
352 } VPU_HWInitFunc;
353
354 typedef struct
355 {
356 MS_U32 u32ApiHW_Version; //<Version of current structure>
357 MS_U16 u16ApiHW_Length; //<Length of this structure>
358
359 MS_U8 u8Cap_Support_Decoder_Num;
360
361 MS_BOOL bCap_Support_MPEG2;
362 MS_BOOL bCap_Support_H263;
363 MS_BOOL bCap_Support_MPEG4;
364 MS_BOOL bCap_Support_DIVX311;
365 MS_BOOL bCap_Support_DIVX412;
366 MS_BOOL bCap_Support_FLV;
367 MS_BOOL bCap_Support_VC1ADV;
368 MS_BOOL bCap_Support_VC1MAIN;
369
370 MS_BOOL bCap_Support_RV8;
371 MS_BOOL bCap_Support_RV9;
372 MS_BOOL bCap_Support_H264;
373 MS_BOOL bCap_Support_AVS;
374 MS_BOOL bCap_Support_AVS_PLUS;
375 MS_BOOL bCap_Support_MJPEG;
376 MS_BOOL bCap_Support_MVC;
377 MS_BOOL bCap_Support_VP8;
378 MS_BOOL bCap_Support_VP9;
379 MS_BOOL bCap_Support_HEVC;
380
381 /*New HW Cap and Feature add in struct at the end*/
382 }VDEC_HwCap;
383
384 //-------------------------------------------------------------------------------------------------
385 // Local Functions Prototype
386 //-------------------------------------------------------------------------------------------------
387 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
388 static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
389 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
390
391 //-------------------------------------------------------------------------------------------------
392 // Global Variables
393 //-------------------------------------------------------------------------------------------------
394 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
395 extern MS_BOOL HAL_MVD_InitHW(void);
396 extern MS_BOOL HAL_MVD_DeinitHW(void);
397 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
398 extern MS_BOOL HAL_HVD_EX_DeinitHW(void);
399 extern void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
400 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
401 #if SUPPORT_G2VP9 && defined(VDEC3)
402 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
403 #endif
404 #if defined (__aeon__)
405 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
406 #else
407 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
408 #endif
409
410 //-------------------------------------------------------------------------------------------------
411 // Local Variables
412 //-------------------------------------------------------------------------------------------------
413 #if 0
414
415 static MS_BOOL _bVPUPowered = FALSE;
416 static MS_BOOL _bVPURsted = FALSE;
417 static MS_BOOL _bVPUSingleMode = FALSE;
418 static VPU_EX_DecModCfg _stVPUDecMode;
419
420 static MS_U8 u8TaskCnt = 0;
421
422 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
423
424 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
425 static VPU_EX_Stream _stVPUStream[] =
426 {
427 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
428 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
429 };
430 static VPU_HWInitFunc stHWInitFunc =
431 {
432 &HAL_MVD_InitHW,
433 &HAL_MVD_DeinitHW,
434 &HAL_HVD_EX_InitHW,
435 &HAL_HVD_EX_DeinitHW,
436 };
437
438 #endif
439
440 #if VPU_ENABLE_EMBEDDED_FW_BINARY
441 static const MS_U8 u8HVD_FW_Binary[] = {
442 #include "fwVPU.dat"
443 };
444
445 #if HVD_ENABLE_RV_FEATURE
446 static const MS_U8 u8HVD_VLC_Binary[] = {
447 #include "fwVPU_VLC.dat"
448 };
449 #endif
450 #endif
451
452
453 #ifdef VDEC3
454 typedef struct
455 {
456 MS_BOOL bTSP;
457 MS_U32 u32Used;
458 } BBU_STATE;
459
460 typedef struct
461 {
462 MS_BOOL bTSP;
463 MS_BOOL bUsedbyMVD;
464 MS_U32 u32Used;
465 } SLQ_STATE;
466 #endif
467
468 typedef struct
469 {
470 MS_BOOL _bVPUPowered;
471 MS_BOOL _bVPURsted;
472 MS_BOOL _bVPUSingleMode;
473 VPU_EX_DecModCfg _stVPUDecMode;
474 MS_U8 u8TaskCnt;
475 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
476 #ifdef VDEC3
477 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
478 #else
479 VPU_EX_Stream _stVPUStream[2];
480 #endif
481
482 VPU_HWInitFunc stHWInitFunc;
483
484 MS_BOOL bVpuExReloadFW;
485 MS_BOOL bVpuExLoadFWRlt;
486 MS_VIRT u32VPUSHMAddr; //PA
487 MS_BOOL bEnableVPUSecureMode;
488
489 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
490 MS_BOOL bEnableDymanicFBMode;
491 MS_PHY u32DynamicFBAddress;
492 MS_U32 u32DynamicFBSize;
493 #ifdef VDEC3
494 MS_VIRT u32FWCodeAddr;
495 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
496
497 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
498 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
499 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
500
501 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
502 #endif
503 } VPU_Hal_CTX;
504
505 //global variables
506 VPU_Hal_CTX* pVPUHalContext = NULL;
507 VPU_Hal_CTX gVPUHalContext;
508 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
509 MS_BOOL bVPUMbxInitFlag = 0;
510 MS_U8 u8VPUMbxMsgClass = 0;
511 MBX_Msg VPUReeToTeeMbxMsg;
512 MBX_Msg VPUTeeToReeMbxMsg;
513
514 //-------------------------------------------------------------------------------------------------
515 // Debug Functions
516 //-------------------------------------------------------------------------------------------------
517
518
519 //-------------------------------------------------------------------------------------------------
520 // Local Functions
521 //-------------------------------------------------------------------------------------------------
522
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)523 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
524 {
525 #if HVD_ENABLE_RV_FEATURE
526 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
527 {
528 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
529 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
530 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
531
532 if (pVlcCfg->u32BinSize)
533 {
534 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
535
536 MS_U32 u32Start;
537 MS_U32 u32StartOffset;
538 MS_U8 u8MiuSel;
539
540 // Get MIU selection and offset from physical address = 0x30000000
541 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
542
543
544 if(u8MiuSel == E_CHIP_MIU_0)
545 cpyflag = E_SPIDMA_DEV_MIU0;
546 else if(u8MiuSel == E_CHIP_MIU_1)
547 cpyflag = E_SPIDMA_DEV_MIU1;
548 else if(u8MiuSel == E_CHIP_MIU_2)
549 cpyflag = E_SPIDMA_DEV_MIU2;
550
551 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
552 {
553 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
554 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
555
556 return FALSE;
557 }
558 }
559 else
560 {
561 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
562 return FALSE;
563 }
564 #else
565 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
566 return FALSE;
567 #endif
568 }
569 else
570 {
571 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
572 {
573 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
574 {
575 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
576 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
577
578 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
579 BDMA_Result bdmaRlt;
580 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
581
582 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
583 u32SrcAdd = pVlcCfg->u32BinAddr;
584 u32tabsize = pVlcCfg->u32BinSize;
585 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
586 MsOS_FlushMemory();
587 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
588
589 if (E_BDMA_OK != bdmaRlt)
590 {
591 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
592 }
593 #else
594 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
595 #endif
596 }
597 else
598 {
599 VPU_MSG_ERR
600 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
601 return FALSE;
602 }
603 }
604 else
605 {
606 #if VPU_ENABLE_EMBEDDED_FW_BINARY
607 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
608 MS_U8 *pu8HVD_VLC_Binary;
609
610 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
611
612 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
613 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
614 (MS_U32) sizeof(u8HVD_VLC_Binary));
615
616 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
617 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
618 #else
619 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
620 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
621 (MS_U32) sizeof(u8HVD_VLC_Binary));
622
623 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
624 #endif
625 #else
626 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
627 return FALSE;
628 #endif
629 }
630 }
631 #endif
632
633 return TRUE;
634 }
635
636 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)637 static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
638 {
639 MS_U8 u8OffsetIdx = 0;
640 MS_U8 u8VSidBaseMask = 0xF0;
641 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
642
643 switch (eVSidBase)
644 {
645 case E_HAL_VPU_MAIN_STREAM_BASE:
646 {
647 u8OffsetIdx = 0;
648 break;
649 }
650 case E_HAL_VPU_SUB_STREAM_BASE:
651 {
652 u8OffsetIdx = 1;
653 break;
654 }
655 case E_HAL_VPU_MVC_STREAM_BASE:
656 {
657 u8OffsetIdx = 0;
658 break;
659 }
660 #ifdef VDEC3
661 case E_HAL_VPU_N_STREAM_BASE:
662 {
663 u8OffsetIdx = u32Id & 0x0F;
664 break;
665 }
666 #endif
667 default:
668 {
669 u8OffsetIdx = 0;
670 break;
671 }
672 }
673
674 /*
675 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
676 u32Id, eVSidBase, u8OffsetIdx);
677 */
678 return u8OffsetIdx;
679 }
680
_VPU_EX_Context_Init(void)681 static void _VPU_EX_Context_Init(void)
682 {
683 #ifdef VDEC3
684 MS_U8 i;
685
686 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
687 {
688 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
689 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
690 }
691
692 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
693 {
694 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
695 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
696 }
697
698 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
699 {
700 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
701 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
702 }
703
704 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
705 {
706 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
707 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
708 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
709 }
710 #else
711 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
712 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
713 #endif
714 pVPUHalContext->bVpuExReloadFW = TRUE;
715 }
716
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)717 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
718 {
719 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
720 MS_U8 u8OffsetIdx = 0;
721
722 if (NULL == pTaskInfo)
723 {
724 return eCmd;
725 }
726
727 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
728
729 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
730 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
731
732 #ifdef VDEC3
733 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
734 {
735 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
736 {
737 eCmd = E_NST_CMD_TASK_MVD_TSP;
738 }
739 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
740 {
741 eCmd = E_NST_CMD_TASK_MVD_SLQ;
742 }
743 }
744 #else
745 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
746 {
747 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
748 {
749 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
750 }
751 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
752 {
753 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
754 }
755 }
756 #endif
757 #ifdef VDEC3
758 #if SUPPORT_G2VP9
759 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
760 #else
761 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
762 #endif
763 {
764 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
765 {
766 eCmd = E_NST_CMD_TASK_HVD_TSP;
767 }
768 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
769 {
770 eCmd = E_NST_CMD_TASK_HVD_BBU;
771 }
772 }
773 #else
774 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
775 {
776 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
777 {
778 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
779 }
780 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
781 {
782 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
783 }
784 }
785 #endif
786
787 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
788 return eCmd;
789 }
790
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)791 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
792 {
793 if (!pTaskInfo)
794 {
795 VPU_MSG_ERR("null input\n");
796 return FALSE;
797 }
798
799 //Check if we need to init MVD HW
800 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
801 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
802 {
803 //Init HW
804 if (FALSE == HAL_VPU_EX_MVDInUsed())
805 {
806 if (TRUE != HAL_MVD_InitHW())
807 {
808 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
809 return FALSE;
810 }
811 }
812 else
813 {
814 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
815 }
816 }
817
818 //MVD use sub mvop
819 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
820 #ifdef VDEC3
821 (pTaskInfo->u8HalId == 1) )
822 #else
823 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
824 #endif
825 {
826 VPU_MSG_ERR("Force turn on HVD\n");
827 if(!HAL_VPU_EX_HVDInUsed())
828 {
829 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
830 {
831 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
832 {
833 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
834 return FALSE;
835 }
836 }
837 else
838 {
839 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
840 HAL_HVD_EX_PowerCtrl(TRUE);
841 }
842 }
843 else
844 {
845 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
846 }
847 }
848
849 //Check if we need to init HVD HW
850 #ifdef VDEC3
851 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
852 #else
853 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
854 #endif
855 {
856 if (!HAL_VPU_EX_MVDInUsed())
857 {
858 if (!HAL_MVD_InitHW())
859 {
860 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
861 return FALSE;
862 }
863 }
864
865 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
866 {
867 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
868 return FALSE;
869 }
870 }
871
872 #if SUPPORT_G2VP9 && defined(VDEC3)
873 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
874 {
875 if (!HAL_VPU_EX_MVDInUsed())
876 {
877 if (!HAL_MVD_InitHW())
878 {
879 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
880 return FALSE;
881 }
882 }
883 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
884 {
885 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
886 return FALSE;
887 }
888 }
889 #endif
890
891 return TRUE;
892 }
893
_VPU_EX_InClock(MS_U32 u32type)894 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
895 {
896 switch (u32type)
897 {
898 case VPU_CLOCK_240MHZ:
899 return 240000000UL;
900 case VPU_CLOCK_216MHZ:
901 return 216000000UL;
902 case VPU_CLOCK_192MHZ:
903 return 192000000UL;
904 case VPU_CLOCK_12MHZ:
905 return 12000000UL;
906 case VPU_CLOCK_320MHZ:
907 return 320000000UL;
908 case VPU_CLOCK_288MHZ:
909 return 288000000UL;
910 case VPU_CLOCK_432MHZ:
911 return 432000000UL;
912 default:
913 return 384000000UL;
914 }
915 }
916
917
918 #if defined(MSOS_TYPE_LINUX)
919 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)920 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
921 {
922 MS_U8 ClassNum = 0;
923 MBX_Result result;
924
925 if (bVPUMbxInitFlag == TRUE)
926 {
927 return TRUE;
928 }
929
930 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
931 {
932 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
933 return FALSE;
934 }
935 else
936 {
937 MApi_MBX_Enable(TRUE);
938 }
939
940 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
941
942 if (E_MBX_SUCCESS != result)
943 {
944 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
945 return FALSE;
946 }
947
948 result = MApi_MBX_RegisterMSG(ClassNum, 10);
949
950 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
951 {
952 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
953 return FALSE;
954 }
955 else
956 {
957 bVPUMbxInitFlag = TRUE;
958 u8VPUMbxMsgClass = ClassNum;
959 return TRUE;
960 }
961 }
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)962 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
963 {
964 MBX_Result result;
965 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
966
967 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
968 {
969 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
970 }
971
972 if (bVPUMbxInitFlag == FALSE)
973 {
974 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
975 }
976
977 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
978 VPUReeToTeeMbxMsg.u8Ctrl = 0;
979 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
980 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
981 VPUReeToTeeMbxMsg.u8Index = msg_type;
982
983 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
984 if (E_MBX_SUCCESS != result)
985 {
986 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
987 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
988 }
989
990 // Receive Reply ACK from TEE side.
991 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
992
993 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
994
995 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
996 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
997 {
998 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
999 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1000 }
1001 else
1002 #else
1003 do
1004 {
1005 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1006 } while(E_MBX_SUCCESS != result);
1007 #endif
1008 {
1009 u8Index = VPUTeeToReeMbxMsg.u8Index;
1010 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1011
1012 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1013 {
1014 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1015 }
1016 }
1017
1018 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1019 }
1020
HAL_VPU_EX_REE_SetSHMBaseAddr(void)1021 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void)
1022 {
1023 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1024 {
1025 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1026 return FALSE;
1027 }
1028 else
1029 {
1030 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1031 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1032 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1033 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1034 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1035 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1036 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1037 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1038
1039 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1040
1041
1042 MS_U32 u32Start;
1043
1044 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1045 {
1046 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1047 pVPUHalContext->u32VPUSHMAddr = u32Start;
1048 }
1049 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1050 {
1051 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1052 pVPUHalContext->u32VPUSHMAddr = u32Start;
1053
1054 }
1055 else // == 0
1056 {
1057 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1058 }
1059 }
1060 return true;
1061 }
1062 #endif
1063
HAL_VPU_EX_GetFWReload(void)1064 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1065 {
1066 return pVPUHalContext->bVpuExReloadFW;
1067 }
1068
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1069 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1070 {
1071 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1072 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1073 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1074 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1075 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1076 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1077 )
1078 {
1079 return FALSE;
1080 }
1081 else
1082 {
1083 return TRUE;
1084 }
1085 }
1086
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1087 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1088 {
1089 MS_PHY u32fwPA = NULL; //physical address
1090 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1091
1092 if (TRUE == HAL_VPU_EX_IsPowered())
1093 {
1094 VPU_MSG_DBG("IsPowered\n");
1095 return TRUE;
1096 }
1097 else
1098 {
1099 //VPU hold
1100 HAL_VPU_EX_SwRst(FALSE);
1101
1102 //VPU clock on
1103 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1104
1105 if (VPU_I_R_ON_MIU0)
1106 VPUInitParams.u8MiuSel = 0;
1107 else if (VPU_I_R_ON_MIU1)
1108 VPUInitParams.u8MiuSel = 1;
1109 else if (VPU_I_R_ON_MIU2)
1110 VPUInitParams.u8MiuSel = 2;
1111
1112 HAL_VPU_EX_Init(&VPUInitParams);
1113 }
1114
1115 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1116 VPU_EX_TaskInfo *pTaskInfo = NULL;
1117 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1118
1119 if (pInitPara)
1120 {
1121 pFWCodeCfg = pInitPara->pFWCodeCfg;
1122 pTaskInfo = pInitPara->pTaskInfo;
1123 pVlcCfg = pInitPara->pVLCCfg;
1124 }
1125 else
1126 {
1127 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1128 return FALSE;
1129 }
1130
1131 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1132 #if defined(MSOS_TYPE_LINUX)
1133 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1134 {
1135 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1136
1137 if (FALSE == HAL_VPU_EX_GetFWReload())
1138 {
1139 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1140 {
1141 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1142 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1143 {
1144 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1145 return FALSE;
1146 }
1147 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1148 }
1149 else
1150 {
1151 //Check f/w prefix "VDEC30"
1152 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1153 {
1154 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1155 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1156 {
1157 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1158 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1159 return FALSE;
1160 }
1161 }
1162 else
1163 {
1164 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1165 }
1166 }
1167 }
1168 else
1169 {
1170 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1171 {
1172 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1173 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1174 return FALSE;
1175 }
1176 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1177 }
1178 }
1179 else
1180 #endif
1181 {
1182 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1183
1184 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1185 {
1186 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1187 return FALSE;
1188 }
1189 }
1190
1191 if (pVlcCfg)
1192 {
1193 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1194 {
1195 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1196 return FALSE;
1197 }
1198 }
1199
1200 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1201 {
1202 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1203 return FALSE;
1204 }
1205
1206 //Init HW
1207 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1208 {
1209 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1210 //_MVD_INIT_FAIL_RET();
1211 return FALSE;
1212 }
1213 else
1214 {
1215 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1216 }
1217
1218 //set vpu clock to FW
1219 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1220 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1221
1222 ctl_ptr->statue = CTL_STU_NONE;
1223 //notify controller the interface version of VPU driver.
1224 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1225 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1226 MsOS_FlushMemory();
1227 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1228
1229 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1230 if (TRUE == HAL_VPU_EX_IsRsted())
1231 {
1232 VPU_MSG_DBG("VPU_IsRsted\n");
1233 return TRUE;
1234 }
1235 else
1236 {
1237 HAL_VPU_EX_SwRstRelse();
1238 }
1239
1240 return TRUE;
1241 }
1242
_VPU_EX_DeinitHW(void)1243 static MS_BOOL _VPU_EX_DeinitHW(void)
1244 {
1245 MS_BOOL bRet = FALSE;
1246
1247 if (FALSE == HAL_VPU_EX_MVDInUsed())
1248 {
1249 bRet = HAL_MVD_DeinitHW();
1250 }
1251
1252 if (FALSE == HAL_VPU_EX_HVDInUsed())
1253 {
1254 bRet = HAL_HVD_EX_DeinitHW();
1255 }
1256 #if SUPPORT_G2VP9 && defined(VDEC3)
1257 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1258 {
1259 bRet = HAL_VP9_EX_DeinitHW();
1260 }
1261 #endif
1262 return bRet;
1263 }
1264
_VPU_EX_DeinitAll(void)1265 static MS_BOOL _VPU_EX_DeinitAll(void)
1266 {
1267 HAL_VPU_EX_SwRst(TRUE);
1268 _VPU_EX_DeinitHW();
1269 HAL_VPU_EX_DeInit();
1270
1271 return TRUE;
1272 }
1273
_VPU_EX_GetActiveCodecCnt(void)1274 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1275 {
1276 MS_U32 i;
1277 MS_U8 u8ActiveCnt = 0;
1278 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1279 {
1280 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1281 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1282 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1283 {
1284 u8ActiveCnt++;
1285 }
1286 }
1287 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1288 {
1289 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1290 }
1291 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1292 return u8ActiveCnt;
1293 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1294 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1295 {
1296 if (TRUE)
1297 {
1298 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1299 }
1300 else
1301 {
1302 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1303 }
1304 }
1305
_VPU_EX_ClockSpeed(MS_U32 u32type)1306 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1307 {
1308 switch (u32type)
1309 {
1310 case VPU_CLOCK_240MHZ:
1311 case VPU_CLOCK_216MHZ:
1312 case VPU_CLOCK_192MHZ:
1313 case VPU_CLOCK_12MHZ:
1314 case VPU_CLOCK_320MHZ:
1315 case VPU_CLOCK_288MHZ:
1316 case VPU_CLOCK_384MHZ:
1317 case VPU_CLOCK_432MHZ:
1318 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1319 break;
1320 default:
1321 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1322 break;
1323 }
1324 }
1325 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1326 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1327 {
1328 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1329 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1330 {
1331 return TRUE;
1332 }
1333 return FALSE;
1334 }
1335 #endif
1336
1337
1338 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1339 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1340 {
1341 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1342 {
1343 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1344 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1345 ms_VDECDecompressDeInit();
1346 return TRUE;
1347 }
1348 else
1349 {
1350 return FALSE;
1351 }
1352 }
1353 #endif
1354
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1355 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1356 {
1357 MS_BOOL bRet = TRUE;
1358 pVPUHalContext->_bVPUSingleMode = bEnable;
1359 return bRet;
1360 }
1361
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1362 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1363 {
1364 MS_BOOL bRet = TRUE;
1365 MS_U8 i=0;
1366 if (pstCfg != NULL)
1367 {
1368 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1369 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1370 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1371 {
1372 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1373 }
1374 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1375 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1376 }
1377 else
1378 {
1379 bRet = FALSE;
1380 }
1381 return bRet;
1382 }
1383
1384 //static MS_BOOL bVpuExReloadFW = TRUE;
1385 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1386 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1387 {
1388 pVPUHalContext->bVpuExReloadFW = bReload;
1389 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1390 return TRUE;
1391 }
1392
1393
1394 //-------------------------------------------------------------------------------------------------
1395 // Global Functions
1396 //-------------------------------------------------------------------------------------------------
1397 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1398 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1399 {
1400 #if HVD_ENABLE_RV_FEATURE
1401 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1402 {
1403 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1404 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1405 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1406
1407 if (pVlcCfg->u32BinSize)
1408 {
1409 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1410
1411 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1412 {
1413 cpyflag = E_SPIDMA_DEV_MIU1;
1414 }
1415 else
1416 {
1417 cpyflag = E_SPIDMA_DEV_MIU0;
1418 }
1419
1420 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1421 {
1422 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1423 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1424
1425 return FALSE;
1426 }
1427 }
1428 else
1429 {
1430 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1431 return FALSE;
1432 }
1433 #else
1434 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1435 return FALSE;
1436 #endif
1437 }
1438 else
1439 {
1440 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1441 {
1442 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1443 {
1444 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1445 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1446
1447 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1448 BDMA_Result bdmaRlt;
1449
1450 MsOS_FlushMemory();
1451 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1452
1453 if (E_BDMA_OK != bdmaRlt)
1454 {
1455 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1456 }
1457 #else
1458 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1459 #endif
1460 }
1461 else
1462 {
1463 VPU_MSG_ERR
1464 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1465 return FALSE;
1466 }
1467 }
1468 else
1469 {
1470 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1471 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1472 MS_U8 *pu8HVD_VLC_Binary;
1473
1474 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1475
1476 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1477 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1478 (MS_U32) sizeof(u8HVD_VLC_Binary));
1479
1480 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1481 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1482 #else
1483 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1484 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1485 (MS_U32) sizeof(u8HVD_VLC_Binary));
1486
1487 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1488 #endif
1489 #else
1490 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1491 return FALSE;
1492 #endif
1493 }
1494 }
1495 #endif
1496
1497 return TRUE;
1498 }
1499 #endif
1500 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1501 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1502 #else
1503 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1504 #endif
1505 {
1506 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1507 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1508 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1509 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1510 MS_U32 u32Arg = 0xFFFFFFFF;
1511 MS_U32 u32Timeout = 0;
1512 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1513 MS_U32 u32CmdArg = 0;
1514 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1515 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1516
1517 _HAL_VPU_Entry();
1518 //Check FW buffer size
1519 if (1 == u8Offset)
1520 {
1521 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1522 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1523
1524 if (u32CurFWBuffSize < u32MinFWBuffSize)
1525 {
1526 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1527 _HAL_VPU_Release();
1528 return FALSE;
1529 }
1530 }
1531
1532 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1533 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1534 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1535 {
1536 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1537 }
1538 #ifdef VDEC3
1539 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1540 #endif
1541
1542 if (0 == pVPUHalContext->u8TaskCnt)
1543 {
1544 //No task is created, need to load f/w, etc.
1545 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1546
1547 if (!_VPU_EX_InitAll(pInitPara))
1548 {
1549 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1550 _HAL_VPU_Release();
1551 return FALSE;
1552 }
1553
1554 //Check if controller finish initialization: clear mailbox, etc.
1555 //Need to check it before sending any controller commands!
1556 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1557 while (CTL_STU_NONE == ctl_ptr->statue)
1558 {
1559 if (HVD_GetSysTime_ms() > u32Timeout)
1560 {
1561 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1562 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1563 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1564 MS_U32 t=0;
1565 for (t=0; t<30; t++)
1566 {
1567 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1568 }
1569 _HAL_VPU_Release();
1570 return FALSE;
1571 }
1572
1573 MsOS_ReadMemory();
1574 }
1575
1576 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1577 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1578
1579 }
1580 else
1581 {
1582 if (pVPUHalContext->_bVPUSingleMode)
1583 {
1584 //Show error message
1585 printf("This task will use dram instead of sram!!!\n");
1586 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1587 }
1588
1589 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1590 {
1591 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1592 _HAL_VPU_Release();
1593 return FALSE;
1594 }
1595 if (pInitPara->pVLCCfg)
1596 {
1597 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1598 {
1599 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1600 _HAL_VPU_Release();
1601 return FALSE;
1602 }
1603 }
1604 }
1605
1606
1607 #ifdef VDEC3
1608 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1609 {
1610 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1611
1612 memset(pTemp4,0,sizeof(VDEC_VBBU));
1613
1614 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1615
1616 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1617
1618 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1619
1620 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1621
1622 memset(pTemp2,0,sizeof(CMD_QUEUE));
1623
1624 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1625
1626 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1627
1628 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1629
1630 memset(pTemp3,0,0x2000);
1631
1632 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1633
1634 memset((void*)pVersion,0,0x8);
1635
1636 *pVersion = 1; //0:diu, 1:wb
1637 }
1638
1639 #endif
1640
1641 #if 1 // For TEE
1642 #ifdef VDEC3
1643 #if SUPPORT_G2VP9
1644 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1645 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1646 #else
1647 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1648 #endif
1649 #else
1650 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1651 #endif
1652 {
1653 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1654
1655 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1656 {
1657 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1658 }
1659 else
1660 {
1661 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1662 }
1663
1664 MsOS_FlushMemory();
1665 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1666
1667 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1668 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1669 }
1670 #endif
1671
1672 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1673 {
1674 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1675 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1676
1677 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1678
1679 MsOS_FlushMemory();
1680 }
1681
1682 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1683 {
1684 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1685 //arg=1 to get better performance for single task
1686 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1687 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1688 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1689 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1690 {
1691 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1692 }
1693 }
1694 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1695 {
1696 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1697 {
1698 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1699 {
1700 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1701 u32CmdArg = CTL_MODE_3DTV;
1702 break;
1703 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1704 u32CmdArg = CTL_MODE_3DTV_PROG;
1705 break;
1706 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1707 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1708 break;
1709 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1710 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1711 break;
1712 default:
1713 u32CmdArg = CTL_MODE_3DTV;
1714 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1715 break;
1716 }
1717 }
1718 else
1719 {
1720 u32CmdArg = CTL_MODE_3DWMV;
1721 }
1722 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1723 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1724 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1725 {
1726 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1727 }
1728 }
1729 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1730 {
1731 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1732 {
1733 u32CmdArg = CTL_MODE_ONE_STC;
1734 }
1735 else
1736 {
1737 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1738 }
1739 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1740 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1741 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1742 {
1743 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1744 }
1745 }
1746
1747 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1748 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1749 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1750 #ifdef VDEC3
1751 {
1752 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1753 }
1754 #else
1755 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1756 #endif
1757
1758 #ifdef VDEC3
1759 #if SUPPORT_G2VP9
1760 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1761 #else
1762 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1763 #endif
1764 {
1765 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1766 }
1767 #else
1768 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1769 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1770 #endif
1771 else
1772 {
1773 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1774 _HAL_VPU_Release();
1775 return FALSE;
1776 }
1777 #else
1778 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1779 #endif
1780
1781 VPRINTF("[%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1782 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1783
1784 MsOS_ReadMemory();
1785 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1786 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1787
1788 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1789 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1790 {
1791 if (HVD_GetSysTime_ms() > u32Timeout)
1792 {
1793 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1794 MS_U32 t=0;
1795 for (t=0; t<30; t++)
1796 {
1797 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1798 }
1799 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1800 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1801 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1802 _HAL_VPU_Release();
1803 return FALSE;
1804 //#endif
1805 }
1806
1807 MsOS_ReadMemory();
1808 }
1809
1810 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1811 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1812
1813 #ifdef VDEC3
1814 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1815 #else
1816 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1817 #endif
1818 {
1819 HAL_HVD_EX_SetBufferAddr(u32Id);
1820 }
1821
1822 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1823 {
1824 eDecType = E_VPU_EX_DECODER_MVD;
1825 }
1826 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1827 {
1828 eDecType = E_VPU_EX_DECODER_HVD;
1829 }
1830 #ifdef VDEC3
1831 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1832 {
1833 eDecType = E_VPU_EX_DECODER_EVD;
1834 }
1835 #if SUPPORT_G2VP9
1836 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1837 {
1838 eDecType = E_VPU_EX_DECODER_G2VP9;
1839 }
1840 #endif
1841 #endif
1842 else
1843 {
1844 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1845 _HAL_VPU_Release();
1846 return FALSE;
1847 }
1848
1849 #ifdef VDEC3
1850 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1851 {
1852 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1853 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1854 }
1855 #endif
1856
1857 if (pTaskInfo->eDecType != eDecType)
1858 {
1859 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1860 pTaskInfo->eDecType, eDecType);
1861 }
1862 goto _SAVE_DEC_TYPE;
1863
1864 _SAVE_DEC_TYPE:
1865 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1866 {
1867 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1868 }
1869 else
1870 {
1871 VPU_MSG_ERR("Cannot save eDecType!!\n");
1872 }
1873
1874 (pVPUHalContext->u8TaskCnt)++;
1875 _HAL_VPU_Release();
1876 return TRUE;
1877 }
1878
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1879 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1880 {
1881 HVD_Return eRet;
1882 #ifdef VDEC3
1883 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
1884 #else
1885 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
1886 #endif
1887 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1888 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
1889
1890 _HAL_VPU_Entry();
1891 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
1892
1893 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
1894 if(eRet != E_HVD_RETURN_SUCCESS)
1895 {
1896 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
1897 }
1898
1899 {
1900 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1901 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1902 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1903
1904 MsOS_ReadMemory();
1905
1906 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1907 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1908
1909 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
1910 {
1911 if (HVD_GetSysTime_ms() > u32Timeout)
1912 {
1913 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
1914 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1915 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
1916
1917 if(pVPUHalContext->u8TaskCnt == 1)
1918 {
1919 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
1920 break;
1921 }
1922 else if(pVPUHalContext->u8TaskCnt == 2)
1923 {
1924 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
1925 _HAL_VPU_Release();
1926 return FALSE;
1927 }
1928 else
1929 {
1930 VPU_MSG_ERR("Task number is not correct\n");
1931 _HAL_VPU_Release();
1932 return FALSE;
1933 }
1934 }
1935
1936 MsOS_ReadMemory();
1937 }
1938
1939 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1940 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1941 }
1942
1943 #if SUPPORT_EVD
1944 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
1945 {
1946 HAL_EVD_EX_ClearTSPInput(u32Id);
1947 }
1948 #endif
1949
1950 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
1951 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
1952 {
1953 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
1954 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
1955 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
1956 }
1957
1958 if (pVPUHalContext->u8TaskCnt)
1959 {
1960 (pVPUHalContext->u8TaskCnt)--;
1961 }
1962 else
1963 {
1964 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
1965 }
1966
1967 if (0 == pVPUHalContext->u8TaskCnt)
1968 {
1969 int i;
1970 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
1971 _VPU_EX_DeinitAll();
1972 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
1973 pVPUHalContext->u32VPUSHMAddr = 0;
1974
1975 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
1976 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
1977 }
1978 else
1979 {
1980 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
1981 _VPU_EX_DeinitHW();
1982 }
1983
1984 _HAL_VPU_Release();
1985 return TRUE;
1986 }
1987
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)1988 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
1989 {
1990 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
1991 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
1992 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
1993 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
1994 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
1995 #endif
1996
1997 if (FALSE == HAL_VPU_EX_GetFWReload())
1998 {
1999 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2000 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2001 {
2002 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2003 }
2004 else
2005 {
2006 //Check f/w prefix "VDEC30"
2007 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2008 {
2009 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2010 }
2011 else
2012 {
2013 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2014 return TRUE;
2015 }
2016 }
2017 }
2018
2019 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2020 {
2021 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2022 if (u32Size != 0)
2023 {
2024 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2025
2026
2027 MS_U32 u32Start;
2028 MS_U32 u32StartOffset;
2029 MS_U8 u8MiuSel;
2030
2031 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2032
2033
2034 if(u8MiuSel == E_CHIP_MIU_0)
2035 cpyflag = E_SPIDMA_DEV_MIU0;
2036 else if(u8MiuSel == E_CHIP_MIU_1)
2037 cpyflag = E_SPIDMA_DEV_MIU1;
2038 else if(u8MiuSel == E_CHIP_MIU_2)
2039 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2040
2041 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2042 {
2043 goto _load_code_fail;
2044 }
2045 }
2046 else
2047 {
2048 goto _load_code_fail;
2049 }
2050 #else
2051 goto _load_code_fail;
2052 #endif
2053 }
2054 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2055 {
2056 if (u32BinAddr != 0 && u32Size != 0)
2057 {
2058 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2059 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2060 {
2061 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2062 {
2063 VPU_MSG_INFO("Decompress ok!!!\n");
2064 }
2065 else
2066 {
2067 VPU_MSG_INFO("Decompress fail!!!\n");
2068 }
2069 }
2070 else
2071 #endif
2072 {
2073 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2074 }
2075 }
2076 else
2077 {
2078 goto _load_code_fail;
2079 }
2080 }
2081 else
2082 {
2083 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2084 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2085 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2086 (MS_U32) sizeof(u8HVD_FW_Binary));
2087
2088 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2089 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2090 {
2091 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2092 {
2093 VPU_MSG_INFO("Decompress ok!!!\n");
2094 }
2095 else
2096 {
2097 VPU_MSG_INFO("Decompress fail!!!\n");
2098 }
2099 }
2100 else
2101 #endif
2102 {
2103 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2104 }
2105 #else
2106 goto _load_code_fail;
2107 #endif
2108 }
2109
2110 MAsm_CPU_Sync();
2111 MsOS_FlushMemory();
2112
2113 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2114 {
2115 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2116 goto _load_code_fail;
2117 }
2118
2119 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2120 return TRUE;
2121
2122 _load_code_fail:
2123 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2124 return FALSE;
2125 }
2126
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2127 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2128 {
2129 u32VPURegOSBase = u32RegBase;
2130 }
2131
HAL_VPU_EX_Init_Share_Mem(void)2132 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2133 {
2134 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2135
2136 MS_U32 u32ShmId;
2137 MS_VIRT u32Addr;
2138 MS_U32 u32BufSize;
2139
2140
2141 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2142 sizeof(VPU_Hal_CTX),
2143 &u32ShmId,
2144 &u32Addr,
2145 &u32BufSize,
2146 MSOS_SHM_QUERY))
2147 {
2148 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2149 sizeof(VPU_Hal_CTX),
2150 &u32ShmId,
2151 &u32Addr,
2152 &u32BufSize,
2153 MSOS_SHM_CREATE))
2154 {
2155 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2156 if(pVPUHalContext == NULL)
2157 {
2158 pVPUHalContext = &gVPUHalContext;
2159 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2160 _VPU_EX_Context_Init();
2161 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2162 }
2163 else
2164 {
2165 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2166 }
2167 //return FALSE;
2168 }
2169 else
2170 {
2171 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2172 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2173 _VPU_EX_Context_Init();
2174 }
2175 }
2176 else
2177 {
2178 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2179 }
2180 #else
2181 if(pVPUHalContext == NULL)
2182 {
2183 pVPUHalContext = &gVPUHalContext;
2184 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2185 _VPU_EX_Context_Init();
2186 }
2187 #endif
2188
2189 return TRUE;
2190
2191 }
2192
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2193 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2194 {
2195 MS_U32 i = 0;
2196
2197 _HAL_VPU_MutexCreate();
2198
2199 _HAL_VPU_Entry();
2200
2201 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2202 {
2203 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2204 {
2205 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2206 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2207 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2208 _HAL_VPU_Release();
2209 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2210 }
2211 }
2212 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2213 {
2214 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2215 {
2216 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2217 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2218 {
2219 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2220 _HAL_VPU_Release();
2221 return pVPUHalContext->_stVPUStream[i].eStreamId;
2222 }
2223 }
2224 }
2225 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2226 {
2227 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2228 {
2229 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2230 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2231 {
2232 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2233 _HAL_VPU_Release();
2234 return pVPUHalContext->_stVPUStream[i].eStreamId;
2235 }
2236 }
2237 }
2238 #ifdef VDEC3
2239 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2240 {
2241 #if 1 // bound FW task to main/sub stream
2242 i = eStreamType - E_HAL_VPU_N_STREAM;
2243 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2244 {
2245 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2246 _HAL_VPU_Release();
2247 return pVPUHalContext->_stVPUStream[i].eStreamId;
2248 }
2249 #else // dynamic select FW task id
2250 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2251 {
2252 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2253 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2254 {
2255 return pVPUHalContext->_stVPUStream[i].eStreamId;
2256 }
2257 }
2258 #endif
2259 }
2260 #endif
2261
2262 _HAL_VPU_Release();
2263
2264 return E_HAL_VPU_STREAM_NONE;
2265 }
2266
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2267 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2268 {
2269 if(u8Idx > 2)
2270 {
2271 return FALSE;
2272 }
2273
2274 _HAL_VPU_Entry();
2275
2276 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2277 {
2278 pVPUHalContext->_stVPUStream[u8Idx].eStreamId = E_HAL_VPU_N_STREAM0;
2279 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2280 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2281 }
2282 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2283 {
2284 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2285 }
2286
2287 _HAL_VPU_Release();
2288
2289 return TRUE;
2290 }
2291
HAL_VPU_EX_CheckFreeStream(void)2292 MS_U8 HAL_VPU_EX_CheckFreeStream(void)
2293 {
2294 MS_U8 u8Idx = 0;
2295
2296 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2297 {
2298 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2299 break;
2300 }
2301
2302 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2303 {
2304 VPU_MSG_ERR("all vpu free streams are occupied \n");
2305 return -1;
2306 }
2307
2308 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2309 return u8Idx;
2310 }
2311
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2312 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2313 {
2314 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2315
2316 // enable module
2317 _VPU_EX_ClockInv(InitParams->bClockInv);
2318 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2319 HAL_VPU_EX_PowerCtrl(TRUE);
2320
2321 #if 1 //Create VPU's own mutex
2322 //_HAL_VPU_MutexCreate();
2323 #else
2324 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2325 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2326 #endif
2327
2328 return TRUE;
2329 }
2330
HAL_VPU_EX_DeInit(void)2331 MS_BOOL HAL_VPU_EX_DeInit(void)
2332 {
2333 if (0 != _VPU_EX_GetActiveCodecCnt())
2334 {
2335 VPU_MSG_DBG("do nothing since codec is active.\n");
2336 return TRUE;
2337 }
2338
2339 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2340
2341 HAL_VPU_EX_PowerCtrl(FALSE);
2342 HAL_VPU_EX_SwRelseMAU();
2343 //_HAL_VPU_MutexDelete();
2344
2345 return TRUE;
2346 }
2347
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2348 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2349 {
2350 if (bEnable)
2351 {
2352 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2353 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2354 pVPUHalContext->_bVPUPowered = TRUE;
2355 }
2356 else
2357 {
2358 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2359 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2360 pVPUHalContext->_bVPUPowered = FALSE;
2361 }
2362 }
2363
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2364 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2365 {
2366 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2367 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2368 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2369 VPU_EX_TimerDelayMS(1);
2370 }
2371
2372 ///-----------------------------------------------------------------------------
2373 /// config AVCH264 CPU
2374 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2375 /// @param u8dlend_en \b IN: endian
2376 /// - 1, little endian
2377 /// - 0, big endian
2378 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2379 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2380 {
2381 MS_BOOL bRet = TRUE;
2382 MS_U32 u32Offset = 0;
2383 MS_U16 tempreg = 0;
2384 MS_U8 u8MiuSel;
2385 //MS_U32 u32TmpStartOffset;
2386
2387 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2388
2389 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2390 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2391 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2392 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2393 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2394 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2395 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2396 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2397 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2398 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2399
2400 #if (HVD_ENABLE_IQMEM)
2401 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2402 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2403 #endif
2404
2405 #if (VPU_FORCE_MIU_MODE)
2406 // Data sram base Unit: byte address
2407 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2408 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2409 // Instruction sram base Unit: byte address
2410 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2411 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2412
2413 #ifndef HAL_FEATURE_MAU
2414 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2415 #endif
2416 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2417
2418 //use force miu mode
2419 if(u8MiuSel == E_CHIP_MIU_0)
2420 {
2421 #ifdef HAL_FEATURE_MAU
2422 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2423 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2424 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2425 #else
2426 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2427 #endif
2428 }
2429 else if(u8MiuSel == E_CHIP_MIU_1)
2430 {
2431 #ifdef HAL_FEATURE_MAU
2432 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2433 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2434 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2435 #else
2436 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2437 #endif
2438 }
2439 else //miu 2
2440 {
2441 #ifdef HAL_FEATURE_MAU
2442 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2443 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2444 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2445 #else
2446 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2447 #endif
2448 }
2449 #else
2450 ///TODO:
2451 #endif
2452
2453
2454 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2455 tempreg |= VPU_REG_IO2_EN;
2456 tempreg |= VPU_REG_QMEM_SPACE_EN;
2457 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2458
2459 return bRet;
2460 }
2461
2462 ///-----------------------------------------------------------------------------
2463 /// Set IQMem data access mode or instruction fetch mode
2464 /// @param u8dlend_en \b IN: endian
2465 /// - 1, switch to data access mode
2466 /// - 0, switch to instruction fetch mode
2467 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2468 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2469 {
2470
2471 if(bEnable){
2472
2473 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2474 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2475
2476 }
2477 else{
2478
2479 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2480
2481 }
2482 }
2483
2484 ///-----------------------------------------------------------------------------
2485 /// H.264 SW reset
2486 /// @return TRUE or FALSE
2487 /// - TRUE, Success
2488 /// - FALSE, Failed
2489 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2490 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2491 {
2492 MS_U16 tempreg = 0, tempreg1 = 0;
2493 #ifndef HAL_FEATURE_MAU
2494 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2495 tempreg |= VPU_REG_CPU_STALL_EN;
2496 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2497
2498 MS_U32 idle_cnt = 100;// ms
2499 while (idle_cnt)
2500 {
2501 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2502 {
2503 break;
2504 }
2505 idle_cnt--;
2506 MsOS_DelayTask(1);
2507 }
2508
2509 if (idle_cnt == 0)
2510 {
2511 printf("ISB ICU idle time out~~~~~\n");
2512 }
2513
2514 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2515 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2516 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2517 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2518
2519 MS_U32 idle_cnt_1 = 100;// ms
2520 while (idle_cnt_1)
2521 {
2522 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2523 {
2524 break;
2525 }
2526 idle_cnt_1--;
2527 MsOS_DelayTask(1);
2528 }
2529
2530 if (idle_cnt_1 == 0)
2531 {
2532 printf("BIU DCU idle time out~~~~~\n");
2533 }
2534
2535 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2536 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2537 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2538 VPU_EX_TimerDelayMS(1);
2539 tempreg &= ~VPU_REG_CPU_R2_EN;
2540 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2541 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2542
2543 #else
2544 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2545
2546 if (bCheckMauIdle)
2547 {
2548 MS_U32 mau_idle_cnt = 100;// ms
2549 while (mau_idle_cnt)
2550 {
2551 if (TRUE == _VPU_EX_MAU_IDLE())
2552 {
2553 break;
2554 }
2555 mau_idle_cnt--;
2556 MsOS_DelayTask(1);
2557 }
2558
2559 if (mau_idle_cnt == 0)
2560 {
2561 printf("MAU idle time out~~~~~\n");
2562 }
2563 }
2564
2565
2566 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2567
2568 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2569 tempreg1 |= MAU1_REG_SW_RESET;
2570 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2571
2572 #if defined(UDMA_FPGA_ENVI)
2573 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2574 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2575 #endif
2576
2577 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2578 tempreg &= ~VPU_REG_CPU_R2_EN;
2579 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2580 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2581 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2582 #endif
2583 VPU_EX_TimerDelayMS(1);
2584 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2585
2586 pVPUHalContext->_bVPURsted = FALSE;
2587 return TRUE;
2588 }
2589
2590 ///-----------------------------------------------------------------------------
2591 /// CPU reset release
2592 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2593 void HAL_VPU_EX_SwRstRelse(void)
2594 {
2595 MS_U16 tempreg = 0;
2596
2597 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2598 tempreg &= ~VPU_REG_CPU_STALL_EN;
2599 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2600
2601 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2602 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2603 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2604 VPU_EX_TimerDelayMS(1);
2605 tempreg |= VPU_REG_CPU_SW_RSTZ;
2606 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2607 VPU_EX_TimerDelayMS(1);
2608 tempreg |= VPU_REG_CPU_R2_EN;
2609 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2610 #ifdef HAL_FEATURE_MAU
2611 MS_U16 tempreg1 = 0;
2612 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2613 tempreg1 &= ~MAU1_REG_SW_RESET;
2614 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2615 #endif
2616 pVPUHalContext->_bVPURsted = TRUE;
2617 }
2618
HAL_VPU_EX_SwRelseMAU(void)2619 void HAL_VPU_EX_SwRelseMAU(void)
2620 {
2621
2622 #ifdef HAL_FEATURE_MAU
2623 MS_U16 tempreg = 0;
2624 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2625 tempreg &= ~MAU1_REG_SW_RESET;
2626 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2627 #endif
2628 }
2629
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2630 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2631 {
2632 MS_U32 u32value = 0;
2633
2634 return u32value;
2635 }
2636
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2637 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2638 {
2639 MS_BOOL bRet = TRUE;
2640
2641 return bRet;
2642 }
2643
2644 ///-----------------------------------------------------------------------------
2645 /// Check AVCH264 Ready or not
2646 /// @return TRUE or FALSE
2647 /// - TRUE, MailBox is free
2648 /// - FALSE, MailBox is busy
2649 /// @param u8MBox \b IN: MailBox to check
2650 /// - AVCH264_HI_MBOX0,
2651 /// - AVCH264_HI_MBOX1,
2652 /// - AVCH264_RISC_MBOX0,
2653 /// - AVCH264_RISC_MBOX1,
2654 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2655 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2656 {
2657 MS_BOOL bResult = FALSE;
2658
2659 switch (u32type)
2660 {
2661 case VPU_HI_MBOX0:
2662 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2663 break;
2664 case VPU_HI_MBOX1:
2665 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2666 break;
2667 case VPU_RISC_MBOX0:
2668 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2669 break;
2670 case VPU_RISC_MBOX1:
2671 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2672 break;
2673 default:
2674 break;
2675 }
2676 return bResult;
2677 }
2678
2679
2680 ///-----------------------------------------------------------------------------
2681 /// Read message from AVCH264
2682 /// @return TRUE or FALSE
2683 /// - TRUE, success
2684 /// - FALSE, failed
2685 /// @param u8MBox \b IN: MailBox to read
2686 /// - AVCH264_RISC_MBOX0
2687 /// - AVCH264_RISC_MBOX1
2688 /// @param u32Msg \b OUT: message read
2689 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2690 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2691 {
2692 MS_BOOL bResult = TRUE;
2693
2694 switch (u32type)
2695 {
2696 case VPU_HI_MBOX0:
2697 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
2698 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
2699 break;
2700 case VPU_HI_MBOX1:
2701 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
2702 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
2703 break;
2704 case VPU_RISC_MBOX0:
2705 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
2706 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
2707 break;
2708 case VPU_RISC_MBOX1:
2709 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
2710 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
2711 break;
2712 default:
2713 *u32Msg = 0;
2714 bResult = FALSE;
2715 break;
2716 }
2717 return bResult;
2718 }
2719
2720 ///-----------------------------------------------------------------------------
2721 /// Mailbox from AVCH264 clear bit resest
2722 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)2723 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
2724 {
2725 switch (u32type)
2726 {
2727 case VPU_RISC_MBOX0:
2728 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
2729 break;
2730 case VPU_RISC_MBOX1:
2731 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
2732 break;
2733 default:
2734 break;
2735 }
2736 }
2737
2738 ///-----------------------------------------------------------------------------
2739 /// Send message to AVCH264
2740 /// @return TRUE or FALSE
2741 /// - TRUE, Success
2742 /// - FALSE, Failed
2743 /// @param u8MBox \b IN: MailBox
2744 /// - AVCH264_HI_MBOX0,
2745 /// - AVCH264_HI_MBOX1,
2746 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)2747 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
2748 {
2749 MS_BOOL bResult = TRUE;
2750
2751 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
2752
2753 switch (u32type)
2754 {
2755 case VPU_HI_MBOX0:
2756 {
2757 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
2758 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
2759 break;
2760 }
2761 case VPU_HI_MBOX1:
2762 {
2763 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
2764 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
2765 break;
2766 }
2767 default:
2768 {
2769 bResult = FALSE;
2770 break;
2771 }
2772 }
2773
2774 return bResult;
2775 }
2776
HAL_VPU_EX_GetProgCnt(void)2777 MS_U32 HAL_VPU_EX_GetProgCnt(void)
2778 {
2779
2780 MS_U16 expc_l=0;
2781 MS_U16 expc_h=0;
2782 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
2783 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
2784 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
2785 }
2786
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)2787 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
2788 {
2789 return _VPU_EX_GetOffsetIdx(u32Id);
2790 }
2791
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)2792 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
2793 {
2794 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2795
2796 if (u32ShmAddr == 0)
2797 {
2798 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
2799 }
2800 else
2801 {
2802 if (u8Offset == 0)
2803 {
2804 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
2805 }
2806 else if (u8Offset == 1)
2807 {
2808 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
2809 }
2810 }
2811
2812 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
2813 return;
2814 }
2815
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)2816 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
2817 {
2818 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2819
2820 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
2821 }
2822
2823
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)2824 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
2825 {
2826 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2827 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
2828 MS_VIRT VsyncBridgeOffset = 0;
2829
2830 if (VPUSHMAddr != 0) // TEE project
2831 {
2832 if ((u8Offset == 0) || (u8Offset == 1))
2833 {
2834 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
2835 }
2836 else
2837 {
2838 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2839 }
2840 }
2841 else // normal project
2842 {
2843 if ((u8Offset == 0) || (u8Offset == 1))
2844 {
2845 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
2846 }
2847 else
2848 {
2849 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2850 }
2851 }
2852
2853 return VsyncBridgeOffset;
2854 }
2855
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)2856 MS_U32 HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
2857 {
2858 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2859 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
2860 MS_VIRT VsyncBridgeExtOffset = 0;
2861
2862 if (VPUSHMAddr != 0) // TEE project
2863 {
2864 if ((u8Offset == 0) || (u8Offset == 1))
2865 {
2866 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
2867 }
2868 else
2869 {
2870 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2871 }
2872 }
2873 else // normal project
2874 {
2875 if ((u8Offset == 0) || (u8Offset == 1))
2876 {
2877 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
2878 }
2879 else
2880 {
2881 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2882 }
2883 }
2884
2885 return VsyncBridgeExtOffset;
2886 }
2887
HAL_VPU_EX_IsPowered(void)2888 MS_BOOL HAL_VPU_EX_IsPowered(void)
2889 {
2890 return pVPUHalContext->_bVPUPowered;
2891 }
2892
HAL_VPU_EX_IsRsted(void)2893 MS_BOOL HAL_VPU_EX_IsRsted(void)
2894 {
2895 return pVPUHalContext->_bVPURsted;
2896 }
2897
HAL_VPU_EX_IsEVDR2(void)2898 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
2899 {
2900 #ifdef EVDR2
2901 return TRUE;
2902 #else
2903 return FALSE;
2904 #endif
2905 }
2906
HAL_VPU_EX_MVDInUsed(void)2907 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
2908 {
2909 //MVD is in used for MVD or HVD_TSP mode.
2910 MS_U8 i;
2911 MS_U8 u8UseCnt = 0;
2912
2913 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2914 {
2915 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
2916 #ifdef VDEC3
2917 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
2918 #endif
2919 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
2920 {
2921 u8UseCnt++;
2922 }
2923 }
2924
2925 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
2926
2927 if (u8UseCnt != 0)
2928 {
2929 return TRUE;
2930 }
2931 else
2932 {
2933 return FALSE;
2934 }
2935 }
2936
HAL_VPU_EX_HVDInUsed(void)2937 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
2938 {
2939 //HVD is in used for HVD or MVD in sub stream.
2940 MS_U8 i;
2941 MS_U8 u8UseCnt = 0;
2942 MS_BOOL bMVDTriggerHVD = FALSE;
2943 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2944 {
2945 #ifdef VDEC3
2946 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
2947 (pVPUHalContext->u8HALId[i] == 1) &&
2948 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
2949 #else
2950 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
2951 (E_HAL_VPU_SUB_STREAM0 == pVPUHalContext->_stVPUStream[i].eStreamId) &&
2952 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
2953 #endif
2954
2955 if(bMVDTriggerHVD)
2956 {
2957 VPU_MSG_DBG("%s i:%d eDecodertype:%d u8DecMod:%d\n",__FUNCTION__,i,pVPUHalContext->_stVPUStream[i].eDecodertype,pVPUHalContext->_stVPUDecMode.u8DecMod);
2958 }
2959
2960 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2961 #ifdef VDEC3
2962 ||(E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2963 #endif
2964 ||(TRUE == bMVDTriggerHVD)
2965 )
2966 {
2967 u8UseCnt++;
2968 }
2969 }
2970
2971 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
2972
2973 if (u8UseCnt != 0)
2974 {
2975 return TRUE;
2976 }
2977 else
2978 {
2979 return FALSE;
2980 }
2981 }
2982
2983 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)2984 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
2985 {
2986 MS_U8 i;
2987 MS_U8 u8UseCnt = 0;
2988
2989 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2990 {
2991 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2992 {
2993 u8UseCnt++;
2994 }
2995 }
2996
2997 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
2998
2999 if (u8UseCnt != 0)
3000 {
3001 return TRUE;
3002 }
3003 else
3004 {
3005 return FALSE;
3006 }
3007 }
3008
3009 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3010 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3011 {
3012 MS_U8 i;
3013 MS_U8 u8UseCnt = 0;
3014
3015 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3016 {
3017 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3018 {
3019 u8UseCnt++;
3020 }
3021 }
3022
3023 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3024
3025 if (u8UseCnt != 0)
3026 {
3027 return TRUE;
3028 }
3029 else
3030 {
3031 return FALSE;
3032 }
3033 }
3034 #endif
3035 #endif
3036
3037 //-----------------------------------------------------------------------------
3038 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3039 /// @brief \b Function \b Description: Set debug level
3040 /// @param -elevel \b IN : debug level
3041 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3042 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3043 {
3044 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3045
3046 switch (eLevel)
3047 {
3048 case E_VPU_EX_UART_LEVEL_ERR:
3049 {
3050 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3051 break;
3052 }
3053 case E_VPU_EX_UART_LEVEL_INFO:
3054 {
3055 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3056 break;
3057 }
3058 case E_VPU_EX_UART_LEVEL_DBG:
3059 {
3060 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3061 break;
3062 }
3063 case E_VPU_EX_UART_LEVEL_TRACE:
3064 {
3065 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3066 break;
3067 }
3068 case E_VPU_EX_UART_LEVEL_FW:
3069 {
3070 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3071 break;
3072 }
3073 default:
3074 {
3075 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3076 break;
3077 }
3078 }
3079 }
3080
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3081 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3082 {
3083 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3084 MS_U32 u32CmdArg = (MS_U32)eVerType;
3085 MS_U32 u32Version = 0xFFFFFFFF;
3086 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3087 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3088 {
3089 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3090 return u32Version;
3091 }
3092
3093 MS_BOOL bRet = false;
3094 MS_U32 u32TimeOut = 0xFFFFFFFF;
3095
3096 while(--u32TimeOut)
3097 {
3098 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3099 {
3100 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3101 if (false == bRet)
3102 {
3103 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3104 return u32Version;
3105 }
3106
3107 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3108 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3109 return u32Version;
3110 }
3111 }
3112
3113 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3114
3115 return u32Version;
3116 }
3117
HAL_VPU_EX_NotSupportDS(void)3118 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3119 {
3120 return FALSE;
3121 }
3122
3123 //-----------------------------------------------------------------------------
3124 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3125 /// @brief \b Function \b Description: Get VPU MIU base address
3126 /// @return - vpu MIU1 base
3127 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3128 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3129 {
3130 return VPU_MIU1BASE_ADDR;
3131 }
3132
3133
HAL_VPU_EX_GetSHMAddr(void)3134 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3135 {
3136 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3137 {
3138 return 0;
3139 }
3140 return pVPUHalContext->u32VPUSHMAddr;
3141 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3142 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3143 {
3144 pVPUHalContext->bEnableVPUSecureMode = enable;
3145 return TRUE;
3146 }
3147
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3148 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3149 {
3150 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3151
3152 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3153 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3154 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3155 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3156 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3157 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3158 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3159 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3160
3161 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3162 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3163 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3164 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3165 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3166 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3167 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3168 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3169 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3170 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3171
3172 return TRUE;
3173 }
3174
3175
HAL_VPU_EfuseRead2Byte(MS_VIRT u32Base,MS_U32 u32RegAddr)3176 MS_U16 HAL_VPU_EfuseRead2Byte(MS_VIRT u32Base,MS_U32 u32RegAddr)
3177 {
3178 return ((volatile MS_U16*)(u32Base))[u32RegAddr];
3179 }
3180
HAL_VPU_EfuseWrite2Byte(MS_VIRT u32Base,MS_U32 u32RegAddr,MS_U16 u16Val)3181 MS_U16 HAL_VPU_EfuseWrite2Byte(MS_VIRT u32Base,MS_U32 u32RegAddr, MS_U16 u16Val)
3182 {
3183 return ((volatile MS_U16*)(u32Base))[u32RegAddr] = u16Val;
3184 }
3185 //-----------------------------------------------------------------------------
3186 /// @brief \b Function \b Name: HAL_VPU_EX_Efuse_Support_VPX()
3187 /// @brief \b Function \b Description: For Mazda to turn off VP8/VP9
3188 /// @return - success/fail
3189 //-----------------------------------------------------------------------------
HAL_VPU_EX_Efuse_Support_VPX(void)3190 MS_BOOL HAL_VPU_EX_Efuse_Support_VPX(void)
3191 {
3192 MS_PHY u32NonPMBankSize = 0;
3193 MS_VIRT u32RiuBaseAdd = 0;
3194 MS_U32 reg_val = 0;
3195 MS_U32 u32timeout_count = 0;
3196 #define MAX_TIMEOUT_COUNT 100UL
3197
3198 if (!MDrv_MMIO_GetBASE( &u32RiuBaseAdd, &u32NonPMBankSize, MS_MODULE_PM))
3199 {
3200 VPRINTF("MMIO_GetBASE failure\n");
3201 return FALSE;
3202 }
3203 else
3204 {
3205 VPRINTF("u32RiuBaseAdd=0x%lx\n", (unsigned long)u32RiuBaseAdd);
3206 }
3207
3208 VPU_REG_ADDRESS u16RiuRegEfuseToggle;
3209 u16RiuRegEfuseToggle.reg_bank = 0x20;
3210 u16RiuRegEfuseToggle.reg_offset =0x2c*2;
3211
3212 VPU_REG_ADDRESS u16RiuRegDisableVPX;
3213 u16RiuRegDisableVPX.reg_bank = 0x20;
3214 u16RiuRegDisableVPX.reg_offset = 0x28*2;
3215
3216 HAL_VPU_EfuseWrite2Byte(u32RiuBaseAdd,u16RiuRegDisableVPX.reg__bank_offset,0x21BC);//0x28
3217
3218 while ((HAL_VPU_EfuseRead2Byte(u32RiuBaseAdd,u16RiuRegDisableVPX.reg__bank_offset) & 0x2000UL) != 0)
3219 {
3220 if (u32timeout_count++ > MAX_TIMEOUT_COUNT)
3221 {
3222 VPRINTF ("[Error] %s(%d) Read time out!!\n", __FUNCTION__, __LINE__);
3223 return FALSE;
3224 }
3225 MsOS_DelayTaskUs(10);
3226 }
3227
3228 reg_val = HAL_VPU_EfuseRead2Byte(u32RiuBaseAdd,u16RiuRegEfuseToggle.reg__bank_offset);//0x2c
3229 VPRINTF("\033[1;32m[%s] %d 0x2058UL reg_val = 0x%x \033[m\n",__FUNCTION__,__LINE__,reg_val);
3230
3231 if(reg_val&0x80)//bit 7, regret bit
3232 return TRUE;
3233 else if(reg_val&0x20)//bit 5, disable bit
3234 return FALSE;
3235 else
3236 return TRUE;;
3237 }
3238
3239
3240 //-----------------------------------------------------------------------------
3241 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3242 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3243 /// @return - success/fail
3244 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3245 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3246 {
3247 #define MAX_CAPABILITY_INFO_NUM 8
3248 #define MAX_CODEC_TYPE_NUM 18
3249
3250 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3251 {
3252 //width, height , frmrate, profile, level, version bit rate reserved2
3253 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3254 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3255 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3256 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3257 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3258 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3259 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3260 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3261 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3262 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3263 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3264 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3265 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3266 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3267 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_MVC
3268 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3269 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3270 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3271 };
3272 if(!HAL_VPU_EX_Efuse_Support_VPX() && (E_HVD_EX_CODEC_TYPE_VP9 == eCodecType || E_HVD_EX_CODEC_TYPE_VP8 == eCodecType))
3273 {
3274 return FALSE;
3275 }
3276 if(eCodecType < MAX_CODEC_TYPE_NUM)
3277 {
3278 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3279 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3280 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3281 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3282 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3283 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3284 pCodecCapInfo->u32BitRate = capability[eCodecType][6];
3285 return TRUE;
3286 }
3287 else
3288 {
3289 return FALSE;
3290 }
3291 }
3292
3293 #ifdef VDEC3
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bIsNstreamMode)3294 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode)
3295 {
3296 MS_U32 i, max_bbu_cnt;
3297 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3298
3299 if(pTaskInfo == NULL)
3300 return retBBUId;
3301
3302 BBU_STATE *bbu_state;
3303 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3304 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3305
3306 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3307
3308 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3309
3310 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3311 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3312 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3313
3314 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3315 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3316
3317 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3318 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3319 */
3320 #if 1
3321 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3322 {
3323 if (bTSP)
3324 {
3325 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3326 {
3327 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3328 slq_state[u8TaskId].bTSP = TRUE;
3329 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3330 return u8TaskId;
3331 }
3332 }
3333 else
3334 {
3335 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3336 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3337 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3338 {
3339 if (slq_state[i].u32Used != 0)
3340 {
3341 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3342 {
3343 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3344 }
3345 }
3346 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3347 {
3348 avaliable_bbu_idx = i; // recored the first empty bbu
3349 }
3350 }
3351
3352 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // In Nstream mode, first priority is sharing bbu
3353 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3354 slq_state[shared_bbu_idx].bTSP = FALSE;
3355 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3356 return avaliable_bbu_idx;
3357 }
3358 else if (slq_state[u8TaskId].u32Used == FALSE) { // 2nd priority is task id
3359 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3360 slq_state[u8TaskId].bTSP = FALSE;
3361 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3362 return u8TaskId;
3363 }
3364 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3365 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3366 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3367 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3368 return avaliable_bbu_idx;
3369 }
3370 else {
3371 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3372 }
3373 }
3374 }
3375 #if SUPPORT_G2VP9
3376 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3377 {
3378 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3379 // Don't care the return value, G2_VP9 will not use it.
3380 return 0;
3381 }
3382 #endif
3383 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3384 {
3385 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3386 // Don't care the return value, VP8 will not use it.
3387 return 0;
3388 }
3389 else
3390 {
3391 switch (pTaskInfo->eDecType)
3392 {
3393 case E_VPU_EX_DECODER_EVD:
3394 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3395 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3396 break;
3397 case E_VPU_EX_DECODER_HVD:
3398 case E_VPU_EX_DECODER_RVD:
3399 case E_VPU_EX_DECODER_MVC:
3400 default:
3401 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3402 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3403 break;
3404 }
3405
3406 if (bTSP)
3407 {
3408 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3409 {
3410 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3411 bbu_state[u8TaskId].bTSP = TRUE;
3412 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3413 slq_state[u8TaskId].bTSP = TRUE;
3414 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3415 return u8TaskId;
3416 }
3417 }
3418 else
3419 {
3420 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3421 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3422 for (i = 0; i < max_bbu_cnt; i++)
3423 {
3424 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3425 {
3426 if (bbu_state[i].bTSP == FALSE)
3427 {
3428 shared_bbu_idx = i;
3429 }
3430 }
3431 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3432 {
3433 avaliable_bbu_idx = i;
3434 }
3435 }
3436 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // // In Nstream mode, first priority is sharing bbu
3437 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3438 return shared_bbu_idx;
3439 }
3440 else if (bbu_state[u8TaskId].u32Used == FALSE) { // 2nd priority is task id
3441 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3442 return u8TaskId;
3443 }
3444 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3445 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3446 return avaliable_bbu_idx;
3447 }
3448 else {
3449 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3450 }
3451 }
3452 }
3453 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3454 MS_U32 j;
3455 MS_BOOL Got = FALSE;
3456 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3457 {
3458 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3459 {
3460 if(slq_state[i].u32Used != 0)
3461 {
3462 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3463 {
3464 retBBUId = i;
3465 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3466 slq_state[retBBUId].bTSP = bTSP;
3467 slq_state[retBBUId].bUsedbyMVD = TRUE;
3468 return retBBUId;
3469 }
3470 }
3471 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3472 {
3473 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3474 {
3475 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3476 {
3477 Got = TRUE;
3478 retBBUId = i;
3479 }
3480 }
3481
3482 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3483 {
3484 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3485 {
3486 Got = TRUE;
3487 retBBUId = i;
3488 }
3489 }
3490
3491 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3492 retBBUId = i;
3493 }
3494 }
3495 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3496 {
3497 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3498 slq_state[retBBUId].bTSP = bTSP;
3499 slq_state[retBBUId].bUsedbyMVD = TRUE;
3500 }
3501 }
3502 #if SUPPORT_G2VP9
3503 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3504 {
3505 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3506 // Don't care the return value, G2_VP9 will not use it.
3507 return 0;
3508 }
3509 #endif
3510 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3511 {
3512 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3513 // Don't care the return value, VP8 will not use it.
3514 return 0;
3515 }
3516 else // HVD/EVD case
3517 {
3518 switch (pTaskInfo->eDecType)
3519 {
3520 case E_VPU_EX_DECODER_EVD:
3521 case E_VPU_EX_DECODER_G2VP9:
3522 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3523 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3524 break;
3525 case E_VPU_EX_DECODER_HVD:
3526 case E_VPU_EX_DECODER_RVD:
3527 case E_VPU_EX_DECODER_MVC:
3528 default:
3529 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3530 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3531 break;
3532 }
3533
3534 for (i = 0; i < max_bbu_cnt; i++)
3535 {
3536 if(bbu_state[i].u32Used != 0)
3537 {
3538 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3539 {
3540 retBBUId = i;
3541 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3542 bbu_state[retBBUId].bTSP = bTSP;
3543 return retBBUId;
3544 }
3545 }
3546 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3547 {
3548 if(i < MAX_MVD_SLQ_COUNT)
3549 {
3550 if(!bTSP) //HVD/EVD first MM case
3551 {
3552 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3553 {
3554 retBBUId = i;
3555 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3556 bbu_state[retBBUId].bTSP = bTSP;
3557 return retBBUId;
3558 }
3559
3560 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3561 retBBUId = i;
3562 }
3563 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3564 {
3565 retBBUId = i;
3566 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3567 bbu_state[retBBUId].bTSP = bTSP;
3568 slq_state[retBBUId].bUsedbyMVD = FALSE;
3569 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3570 slq_state[retBBUId].bTSP = bTSP;
3571 return retBBUId;
3572 }
3573 }
3574 }
3575 }
3576 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3577 {
3578 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3579 bbu_state[retBBUId].bTSP = bTSP;
3580 if(bTSP)
3581 {
3582 slq_state[retBBUId].bUsedbyMVD = FALSE;
3583 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3584 slq_state[retBBUId].bTSP = bTSP;
3585 }
3586 }
3587 }
3588 #endif
3589 return retBBUId;
3590 }
3591
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3592 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3593 {
3594 MS_U32 max_bbu_cnt;
3595 BBU_STATE *bbu_state;
3596 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3597
3598 if(pTaskInfo == NULL)
3599 return FALSE;
3600 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3601 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3602
3603 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3604 /* MS_U32 i;
3605 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3606 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3607
3608 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3609 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3610
3611 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3612 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3613 */
3614 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3615 {
3616 // TO DO
3617 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3618 {
3619 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3620 slq_state[u32BBUId].bTSP = FALSE;
3621 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3622 return TRUE;
3623 }
3624 }
3625 #if SUPPORT_G2VP9
3626 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3627 {
3628 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3629 return TRUE;
3630 }
3631 #endif
3632 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3633 {
3634 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3635 return TRUE;
3636 }
3637 else
3638 {
3639 switch (pTaskInfo->eDecType)
3640 {
3641 case E_VPU_EX_DECODER_EVD:
3642 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3643 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3644 break;
3645 case E_VPU_EX_DECODER_HVD:
3646 case E_VPU_EX_DECODER_RVD:
3647 case E_VPU_EX_DECODER_MVC:
3648 default:
3649 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3650 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3651 break;
3652 }
3653
3654 if (u32BBUId < max_bbu_cnt)
3655 {
3656 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
3657 bbu_state[u32BBUId].bTSP = FALSE;
3658 if (bTSP)
3659 {
3660 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3661 slq_state[u32BBUId].bTSP = FALSE;
3662 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3663 }
3664 return TRUE;
3665 }
3666 }
3667 return FALSE;
3668 }
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)3669 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
3670 {
3671 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3672
3673 if (CHECK_NULL_PTR(pstVBBU))
3674 return 0;
3675 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3676 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
3677 MS_U32 u32Vacancy = 0;
3678
3679 if (u32WrPtr == u32RdPtr)
3680 {
3681 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
3682 }
3683 else if (u32WrPtr > u32RdPtr)
3684 {
3685 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
3686 }
3687 else
3688 {
3689 u32Vacancy = u32RdPtr - u32WrPtr - 1;
3690 }
3691
3692 return u32Vacancy;
3693 }
3694
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)3695 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
3696 {
3697 return MAX_VDEC_VBBU_ENTRY_COUNT;
3698 }
3699
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3700 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3701 {
3702 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3703 #if SUPPORT_G2VP9
3704 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3705 #endif
3706
3707 if (CHECK_NULL_PTR(pstVBBU))
3708 return FALSE;
3709 MsOS_ReadMemory();
3710 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
3711
3712 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
3713 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
3714 {
3715 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
3716 }
3717 else
3718 {
3719 #if SUPPORT_G2VP9
3720 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3721 {
3722 if (stEntry->u32Offset == 0)
3723 return 0;
3724 else
3725 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3726 }
3727 else
3728 #endif
3729 {
3730 return stEntry->u32Offset;
3731 }
3732 }
3733 }
3734
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3735 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3736 {
3737 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3738 VDEC_VBBU_Entry *stEntry;
3739 #if SUPPORT_G2VP9
3740 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3741 #endif
3742
3743 MsOS_ReadMemory();
3744 if (CHECK_NULL_PTR(pstVBBU))
3745 return 0;
3746 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3747
3748 if (u32WrPtr == 0)
3749 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
3750 else
3751 u32WrPtr--;
3752
3753 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
3754
3755 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
3756 #if SUPPORT_G2VP9
3757 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3758 {
3759 if (stEntry->u32Offset == 0)
3760 return 0;
3761 else
3762 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3763 }
3764 else
3765 #endif
3766 {
3767 return stEntry->u32Offset + stEntry->u32Length;
3768 }
3769 }
3770
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)3771 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
3772 {
3773 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3774 #if SUPPORT_G2VP9
3775 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3776 #endif
3777
3778 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
3779 return FALSE;
3780 MsOS_ReadMemory();
3781 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
3782 MS_U32 u32NewWrPtr;
3783
3784 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
3785 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
3786 {
3787 u32NewWrPtr = 0;
3788 }
3789
3790 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
3791
3792 stEntry->u32Offset = stVpuPkt->u32Offset;
3793
3794 #if SUPPORT_G2VP9
3795 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3796 {
3797 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3798 }
3799 #endif
3800
3801 stEntry->u32Length = stVpuPkt->u32Length;
3802 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
3803 stEntry->u32ID_H = stVpuPkt->u32ID_H;
3804 stEntry->u32ID_L = stVpuPkt->u32ID_L;
3805
3806 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
3807
3808 pstVBBU->u32WrPtr = u32NewWrPtr;
3809
3810 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
3811
3812 MsOS_FlushMemory();
3813
3814 return TRUE;
3815 }
3816
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)3817 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
3818 {
3819 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3820
3821 if (CHECK_NULL_PTR(pstVBBU))
3822 return FALSE;
3823 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
3824 }
3825
3826 ///-----------------------------------------------------------------------------
3827 /// specify the command send to Mail box or DRAM
3828 /// @return TRUE or FALSE
3829 /// - TRUE, Mail box
3830 /// - FALSE, Dram
3831 /// @param u32Cmd \b IN: Command is going to be sned
3832 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)3833 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
3834 {
3835 MS_BOOL bResult = TRUE;
3836
3837 switch (u32Cmd)
3838 {
3839 // *********** Runtime action Command
3840 /* case E_HVD_CMD_RELEASE_DISPQ:
3841 case E_HVD_CMD_UPDATE_DISPQ:
3842 case E_HVD_CMD_FLUSH_DEC_Q:
3843 case E_HVD_CMD_FLUSH:
3844 case E_HVD_CMD_PLAY:
3845 case E_HVD_CMD_PAUSE:
3846 case E_HVD_CMD_STOP:
3847 case E_HVD_CMD_STEP_DECODE:
3848 case E_HVD_CMD_SKIP_DEC:
3849 case E_HVD_CMD_DISP_I_DIRECT:*/
3850 // *********** Dual-Stream Create Task Command
3851 case E_DUAL_CMD_TASK0_HVD_BBU:
3852 case E_DUAL_CMD_TASK0_HVD_TSP:
3853 case E_DUAL_CMD_TASK0_MVD_SLQ:
3854 case E_DUAL_CMD_TASK0_MVD_TSP:
3855 case E_DUAL_CMD_TASK1_HVD_BBU:
3856 case E_DUAL_CMD_TASK1_HVD_TSP:
3857 case E_DUAL_CMD_MODE:
3858 #ifndef _WIN32
3859 case E_DUAL_CMD_TASK1_MVD_SLQ:
3860 case E_DUAL_CMD_TASK1_MVD_TSP:
3861 #endif
3862 case E_DUAL_CMD_DEL_TASK:
3863 case E_DUAL_CMD_SINGLE_TASK:
3864 case E_DUAL_VERSION:
3865 case E_DUAL_R2_CMD_EXIT:
3866 #ifdef VDEC3
3867 case E_DUAL_R2_CMD_FBADDR:
3868 case E_DUAL_R2_CMD_FBSIZE:
3869 // *********** N-Streams
3870 case E_NST_CMD_TASK_HVD_TSP:
3871 case E_NST_CMD_TASK_HVD_BBU:
3872 case E_NST_CMD_TASK_MVD_TSP:
3873 case E_NST_CMD_TASK_MVD_SLQ:
3874 case E_NST_CMD_DEL_TASK:
3875 #endif
3876 case E_DUAL_CMD_COMMON:
3877 {
3878 bResult = TRUE;
3879 }
3880 break;
3881 default:
3882 {
3883 bResult = FALSE;
3884 }
3885 break;
3886 }
3887
3888 return bResult;
3889 }
3890
3891 ///-----------------------------------------------------------------------------
3892 /// specify the command send to Mail box or DRAM
3893 /// @return TRUE or FALSE
3894 /// - TRUE, Mail box
3895 /// - FALSE, Dram
3896 /// @param u32Cmd \b IN: Command is going to be sned
3897 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)3898 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
3899 {
3900 MS_BOOL bResult = TRUE;
3901
3902 switch (u32Cmd)
3903 {
3904 // *********** Runtime action Command
3905 case E_HVD_CMD_RELEASE_DISPQ:
3906 case E_HVD_CMD_UPDATE_DISPQ:
3907 case E_HVD_CMD_FLUSH_DEC_Q:
3908 case E_HVD_CMD_PAUSE:
3909 case E_HVD_CMD_FLUSH:
3910 case E_HVD_CMD_PLAY:
3911 case E_HVD_CMD_STOP:
3912 case E_HVD_CMD_SKIP_DEC:
3913 case E_HVD_CMD_DISP_I_DIRECT:
3914 case E_HVD_CMD_STEP_DECODE:
3915 case E_HVD_CMD_INC_DISPQ_NUM:
3916 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
3917 {
3918 bResult = TRUE;
3919 }
3920 break;
3921 default:
3922 {
3923 bResult = FALSE;
3924 }
3925 break;
3926 }
3927
3928 return bResult;
3929 }
3930
3931 ///-----------------------------------------------------------------------------
3932 /// Send message to HVD stream command queue
3933 /// @return TRUE or FALSE
3934 /// - TRUE, Success
3935 /// - FALSE, Failed
3936 /// @param u32DramAddr \b IN: address to be writen
3937 /// @param u32Msg \b IN: data to be writen
3938 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)3939 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
3940 {
3941 MS_BOOL bResult = TRUE;
3942
3943 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
3944
3945 WRITE_LONG(u32DramAddr,u32Msg);
3946
3947 return bResult;
3948 }
3949
3950 ///-----------------------------------------------------------------------------
3951 /// Read task share memory to specify that task command queue is empty or not
3952 /// @return TRUE or FALSE
3953 /// - TRUE, Empty
3954 /// - FALSE, Non empty
3955 /// @param u32Id \b IN: Task information
3956 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)3957 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
3958 {
3959 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3960 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
3961 if (!cmd_q)
3962 {
3963 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
3964 return FALSE;
3965 }
3966
3967 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
3968 }
3969
3970 ///-----------------------------------------------------------------------------
3971 /// Read task share memory to specify that task command queue is full or not
3972 /// @return TRUE or FALSE
3973 /// - TRUE, Full
3974 /// - FALSE, Non full
3975 /// @param u32Id \b IN: Task information
3976 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)3977 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
3978 {
3979 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3980 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
3981 if (!cmd_q)
3982 {
3983 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
3984 return TRUE;
3985 }
3986 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
3987
3988 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
3989 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
3990
3991 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
3992 }
3993
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)3994 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
3995 {
3996 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
3997 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
3998 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
3999
4000 #if HVD_ENABLE_MVC
4001 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4002 {
4003 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4004 }
4005 #endif
4006
4007 if (CHECK_NULL_PTR(cmd_q))
4008 {
4009 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4010 return bResult;
4011 }
4012 MS_VIRT u32CmdQWdPtr;
4013
4014 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4015 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4016
4017 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4018 return E_HVD_COMMAND_QUEUE_FULL;
4019 else
4020 {
4021 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4022 }
4023
4024 switch (u8CmdType)
4025 {
4026 case E_HVD_CMDQ_CMD:
4027 {
4028 u32Msg |= (u8TaskID << 24);
4029 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4030
4031 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4032
4033 if (bResult)
4034 {
4035 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4036
4037 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4038 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4039
4040 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4041 }
4042 break;
4043 }
4044 case E_HVD_CMDQ_ARG:
4045 {
4046 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4047 if (bResult)
4048 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4049 break;
4050 }
4051 default:
4052 {
4053 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4054 break;
4055 }
4056 }
4057
4058 MsOS_FlushMemory();
4059
4060 return bResult;
4061 }
4062
4063 ///-----------------------------------------------------------------------------
4064 /// Read task share memory to specify that task display command queue is empty or not
4065 /// @return TRUE or FALSE
4066 /// - TRUE, Empty
4067 /// - FALSE, Non empty
4068 /// @param u32Id \b IN: Task information
4069 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4070 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4071 {
4072 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4073 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4074 if (!cmd_q)
4075 {
4076 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4077 return FALSE;
4078 }
4079
4080 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4081 }
4082
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4083 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4084 {
4085 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4086 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4087 if (!cmd_q)
4088 {
4089 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4090 return TRUE;
4091 }
4092
4093 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4094
4095 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4096 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4097
4098 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4099 }
4100
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4101 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4102 {
4103 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4104 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4105 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4106
4107 #if HVD_ENABLE_MVC
4108 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4109 {
4110 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4111 }
4112 #endif
4113
4114 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4115 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4116
4117 if (CHECK_NULL_PTR(cmd_q))
4118 {
4119 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4120 return bResult;
4121 }
4122
4123 MS_VIRT u32DISPCMDQWdPtr;
4124
4125 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4126 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4127
4128 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4129 return E_HVD_COMMAND_QUEUE_FULL;
4130 else
4131 {
4132 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4133 }
4134
4135 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4136
4137 switch (u8CmdType)
4138 {
4139 case E_HVD_CMDQ_CMD:
4140 {
4141 u32Msg |= (u8TaskID << 24);
4142 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4143
4144 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4145
4146 if (bResult)
4147 {
4148 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4149
4150 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4151 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4152
4153 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4154 }
4155 break;
4156 }
4157 case E_HVD_CMDQ_ARG:
4158 {
4159 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4160 if (bResult)
4161 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4162 break;
4163 }
4164 default:
4165 {
4166 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4167 break;
4168 }
4169 }
4170
4171 MsOS_FlushMemory();
4172
4173 return bResult;
4174 }
4175
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4176 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4177 {
4178 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4179 MS_U32 u32StAddr;
4180 MS_U8 u8TmpMiuSel;
4181
4182 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4183
4184 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4185
4186 return TRUE;
4187 }
4188 #endif
4189
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4190 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4191 {
4192 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4193
4194 if(u32address >= HAL_MIU1_BASE)
4195 {
4196 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4197 }
4198 else
4199 {
4200 pVPUHalContext->u32DynamicFBAddress = u32address;
4201 }
4202
4203 pVPUHalContext->u32DynamicFBSize = u32Size;
4204 }
4205
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4206 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4207 {
4208 MS_SIZE FrameBufferSize = 0;
4209
4210 switch(eCodecType)
4211 {
4212 case E_VPU_EX_CODEC_TYPE_MPEG2:
4213 case E_VPU_EX_CODEC_TYPE_H263:
4214 case E_VPU_EX_CODEC_TYPE_MPEG4:
4215 case E_VPU_EX_CODEC_TYPE_DIVX311:
4216 case E_VPU_EX_CODEC_TYPE_DIVX412:
4217 case E_VPU_EX_CODEC_TYPE_FLV:
4218 FrameBufferSize = 0x1E00000;
4219 break;
4220 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4221 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4222 FrameBufferSize = 0x6C00000;
4223 break;
4224 case E_VPU_EX_CODEC_TYPE_RV8:
4225 case E_VPU_EX_CODEC_TYPE_RV9:
4226 FrameBufferSize = 0x1B00000;
4227 break;
4228 case E_VPU_EX_CODEC_TYPE_VP8:
4229 FrameBufferSize = 0x1500000;
4230 break;
4231 case E_VPU_EX_CODEC_TYPE_H264:
4232 FrameBufferSize = 0x8200000;
4233 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4234 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4235 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4236 break;
4237 case E_VPU_EX_CODEC_TYPE_AVS:
4238 FrameBufferSize = 0x1B00000;
4239 break;
4240 case E_VPU_EX_CODEC_TYPE_MJPEG:
4241 FrameBufferSize = 0x2800000;
4242 break;
4243 case E_VPU_EX_CODEC_TYPE_MVC:
4244 FrameBufferSize = 0x4200000;
4245 break;
4246 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4247 FrameBufferSize = 0xB000000;
4248 break;
4249 case E_VPU_EX_CODEC_TYPE_HEVC:
4250 #if SUPPORT_MSVP9
4251 case E_VPU_EX_CODEC_TYPE_VP9:
4252 #endif
4253 FrameBufferSize = 0xA000000;
4254 break;
4255 #if !SUPPORT_MSVP9
4256 case E_VPU_EX_CODEC_TYPE_VP9:
4257 FrameBufferSize = 0x7800000;
4258 break;
4259 #endif
4260 default:
4261 FrameBufferSize = 0;
4262 break;
4263 }
4264
4265 return FrameBufferSize;
4266 }
4267
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4268 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4269 {
4270 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4271 }
4272
4273 #ifdef CMA_DRV_DIRECT_INIT
4274 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4275 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4276 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4277 {
4278 MS_SIZE FrameBufferSize = 0;
4279
4280 if (!offset || !length)
4281 return FALSE;
4282
4283 total_length -= unUseSize;
4284 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4285 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4286
4287 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4288
4289 if(FrameBufferSize == 0)
4290 {
4291 return FALSE;
4292 }
4293 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4294 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4295 if (total_length < FrameBufferSize)
4296 {
4297 *offset = unUseSize;
4298 *length = total_length;
4299 }
4300 else // todo, dual decode case
4301 {
4302 *offset = unUseSize;
4303 *length = FrameBufferSize;
4304 }
4305 return TRUE;
4306 }
4307 #endif
4308
4309 #else
4310 #include "halVPU_EX.h"
4311 #include "drvMMIO.h"
4312 #include "../../../../vdec_v2/hal/macan/hvd_ex/regHVD_EX.h"
4313 #include "halCHIP.h"
4314
4315 extern int lib_lowprintf(const char *fmt, ...);
4316 #define PRINTF lib_lowprintf
4317 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
4318 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
4319
4320 MS_U8 u8FW_Binary[] = {
4321 #include "fwVPU.dat"
4322 };
4323
4324 MS_U32 u32HVDRegOSBase;
4325
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)4326 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
4327 {
4328 //PRINTF("do load code,u32DestAddr %x\n",addr);
4329 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
4330 MAsm_CPU_Sync();
4331 MsOS_FlushMemory();
4332
4333 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
4334 {
4335 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
4336 return FALSE;
4337 }
4338 return TRUE;
4339 }
4340
HAL_VPU_EX_SetLockDownRegister(void * param)4341 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
4342 {
4343 #if 1
4344 MS_PHY u32StAddr_main;
4345 MS_PHY u32StAddr_sub;
4346 MS_U32 u32NonPMBankSize = 0;
4347 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
4348
4349 if(param == NULL)
4350 {
4351 return FALSE;
4352 }
4353
4354 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
4355
4356 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
4357
4358 // ES buffer
4359 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
4360 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
4361
4362
4363 MS_PHY u32StartOffset;
4364 MS_U8 u8MiuSel;
4365
4366 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
4367 u32StAddr_main = u32StartOffset;
4368
4369 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
4370 u32StAddr_sub = u32StartOffset;
4371
4372 //Lock down register
4373 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
4374 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
4375
4376 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
4377 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
4378 //~
4379
4380 // Lock Down
4381 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
4382 //~
4383 #endif
4384 return TRUE;
4385 }
4386
4387
4388 #endif
4389