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Searched refs:INNC_REG_BASE (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBC.c133 #define INNC_REG_BASE 0x3800UL macro
1784 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
1935 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_GetSNR()
1944 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_GetSNR()
2266 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_Get_FreqOffset()
2279 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_Get_FreqOffset()
2453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBC.c133 #define INNC_REG_BASE 0x2A00 macro
1777 u16Address = INNC_REG_BASE + 0x50; //TR lock indicator, in INTERN_DVBC_GetLock()
1928 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_GetSNR()
1937 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_GetSNR()
2245 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_Get_FreqOffset()
2258 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_Get_FreqOffset()
2415 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x4A, 0x00); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2416 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2419 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2421 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBC.c133 #define INNC_REG_BASE 0x2A00 macro
1803 u16Address = INNC_REG_BASE + 0x50; //TR lock indicator, in INTERN_DVBC_GetLock()
1954 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_GetSNR()
1963 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_GetSNR()
2270 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80); in INTERN_DVBC_Get_FreqOffset()
2283 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00); in INTERN_DVBC_Get_FreqOffset()
2440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x4A, 0x00); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2441 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBC.c133 #define INNC_REG_BASE 0x2600UL macro
1339 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
1982 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1983 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1997 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2161 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x2600UL macro
1798 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2462 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2469 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2476 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2642 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBC.c132 #define INNC_REG_BASE 0x2600 macro
1537 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2176 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2177 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2180 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2182 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2191 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2355 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBC.c132 #define INNC_REG_BASE 0x2600UL macro
1343 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
1986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1987 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
1996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2001 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetCurrentSymbolRateOffset()
2165 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c138 #define INNC_REG_BASE 0x2600UL // P2 = 1, 0x11b00 -> 0x1b00 macro
2810 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_GetSNR()
2970 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_GetSNR()
3746 … MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp); in INTERN_DVBC_info()
3748 … MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp); in INTERN_DVBC_info()
3750 … MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1442 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2295 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2297 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2299 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1442 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2295 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2297 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2299 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBC.c135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00 macro
1392 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in INTERN_DVBC_GetLock()
2245 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp); in INTERN_DVBC_info()
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp); in INTERN_DVBC_info()
2249 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp); in INTERN_DVBC_info()
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dvb_extdemod/
H A DdrvDMD_EXTERN_MSB201X.c162 #define INNC_REG_BASE 0x2900 macro
2708 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x80); in _MDrv_DMD_MSB201X_GetSNR()
2717 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x00); in _MDrv_DMD_MSB201X_GetSNR()
3872 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator, in _MDrv_DMD_MSB201X_GetLock()
4159 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x80); in _MDrv_DMD_MSB201X_Get_FreqOffset()
4172 status &= _MDrv_DMD_MSB201X_SetReg(devID, INNC_REG_BASE + 0x05, 0x00); in _MDrv_DMD_MSB201X_Get_FreqOffset()