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Searched refs:val (Results 1 – 25 of 1092) sorted by relevance

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/rk3399_rockchip-uboot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ argument
170 ({ unsigned long __value = (val); \
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) argument
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) argument
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) argument
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) argument
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) argument
190 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) argument
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) argument
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) argument
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/rk3399_rockchip-uboot/arch/microblaze/include/asm/
H A Dasm.h10 #define NGET(val, fslnum) \ argument
11 __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
13 #define GET(val, fslnum) \ argument
14 __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
16 #define NCGET(val, fslnum) \ argument
17 __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
19 #define CGET(val, fslnum) \ argument
20 __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
22 #define NPUT(val, fslnum) \ argument
23 __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
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/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dcontrol_regs.h25 unsigned long val; in read_cr0() local
27 asm volatile ("movl %%cr0, %0" : "=r" (val) : : "memory"); in read_cr0()
28 return val; in read_cr0()
31 static inline void write_cr0(unsigned long val) in write_cr0() argument
33 asm volatile ("movl %0, %%cr0" : : "r" (val) : "memory"); in write_cr0()
38 unsigned long val; in read_cr2() local
40 asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : : "memory"); in read_cr2()
41 return val; in read_cr2()
46 unsigned long val; in read_cr3() local
48 asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : : "memory"); in read_cr3()
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H A Dmsr.h64 #define DECLARE_ARGS(val, low, high) unsigned low, high argument
65 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) argument
66 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) argument
67 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) argument
69 #define DECLARE_ARGS(val, low, high) unsigned long long val argument
70 #define EAX_EDX_VAL(val, low, high) (val) argument
71 #define EAX_EDX_ARGS(val, low, high) "A" (val) argument
72 #define EAX_EDX_RET(val, low, high) "=A" (val) argument
78 DECLARE_ARGS(val, low, high); in native_read_msr()
80 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); in native_read_msr()
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/rk3399_rockchip-uboot/drivers/net/phy/
H A Dmv88e61xx.c225 int val; in mv88e61xx_smi_wait() local
229 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
230 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_smi_wait()
293 u16 val) in mv88e61xx_reg_write() argument
303 val); in mv88e61xx_reg_write()
313 SMI_DATA_REG, val); in mv88e61xx_reg_write()
333 int val; in mv88e61xx_phy_wait() local
337 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
339 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_phy_wait()
404 int reg, u16 val) in mv88e61xx_phy_write() argument
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/rk3399_rockchip-uboot/drivers/usb/phy/
H A Domap_usb_phy.c69 u32 val; in omap_usb_dpll_relock() local
73 val = readl(&phy_regs->pll_status); in omap_usb_dpll_relock()
74 if (val & PLL_LOCK) in omap_usb_dpll_relock()
82 u32 val; in omap_usb_dpll_lock() local
88 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
89 val &= ~PLL_REGN_MASK; in omap_usb_dpll_lock()
90 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_usb_dpll_lock()
91 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
93 val = readl(&phy_regs->pll_config_2); in omap_usb_dpll_lock()
94 val &= ~PLL_SELFREQDCO_MASK; in omap_usb_dpll_lock()
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/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dpipe3-phy.c88 u32 val; in omap_pipe3_wait_lock() local
93 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in omap_pipe3_wait_lock()
94 if (val & PLL_LOCK) in omap_pipe3_wait_lock()
98 if (!(val & PLL_LOCK)) { in omap_pipe3_wait_lock()
108 u32 val; in omap_pipe3_dpll_program() local
117 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
118 val &= ~PLL_REGN_MASK; in omap_pipe3_dpll_program()
119 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
120 omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
122 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in omap_pipe3_dpll_program()
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/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dmipsregs.h881 #define write_r10k_perf_cntr(counter,val) \ argument
886 : "r" (val), "i" (counter)); \
900 #define write_r10k_perf_cntl(counter,val) \ argument
905 : "r" (val), "i" (counter)); \
984 #define __write_ulong_c0_register(reg, sel, val) \ argument
987 __write_32bit_c0_register(reg, sel, val); \
989 __write_64bit_c0_register(reg, sel, val); \
1043 #define __write_64bit_c0_split(source, sel, val) \ argument
1057 : : "r" (val)); \
1067 : : "r" (val)); \
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/rk3399_rockchip-uboot/arch/sh/include/asm/
H A Dunaligned-sh4a.h96 static inline void __put_le16_noalign(u8 *p, u16 val) in __put_le16_noalign() argument
98 *p++ = val; in __put_le16_noalign()
99 *p++ = val >> 8; in __put_le16_noalign()
102 static inline void __put_le32_noalign(u8 *p, u32 val) in __put_le32_noalign() argument
104 __put_le16_noalign(p, val); in __put_le32_noalign()
105 __put_le16_noalign(p + 2, val >> 16); in __put_le32_noalign()
108 static inline void __put_le64_noalign(u8 *p, u64 val) in __put_le64_noalign() argument
110 __put_le32_noalign(p, val); in __put_le64_noalign()
111 __put_le32_noalign(p + 4, val >> 32); in __put_le64_noalign()
114 static inline void __put_be16_noalign(u8 *p, u16 val) in __put_be16_noalign() argument
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/rk3399_rockchip-uboot/drivers/usb/ulpi/
H A Dulpi.c34 u32 val, tval = ULPI_TEST_VALUE; in ulpi_integrity_check() local
43 val = ulpi_read(ulpi_vp, &ulpi->scratch); in ulpi_integrity_check()
44 if (val != tval) { in ulpi_integrity_check()
46 return val; in ulpi_integrity_check()
55 u32 val, id = 0; in ulpi_init() local
61 val = ulpi_read(ulpi_vp, reg - i); in ulpi_init()
62 if (val == ULPI_ERROR) in ulpi_init()
63 return val; in ulpi_init()
65 id = (id << 8) | val; in ulpi_init()
77 u32 val; in ulpi_select_transceiver() local
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/rk3399_rockchip-uboot/arch/arm/mach-uniphier/
H A Dmemconf.c20 u32 val = 0; in __uniphier_memconf_init() local
26 val |= SG_MEMCONF_CH0_NUM_1; in __uniphier_memconf_init()
30 val |= SG_MEMCONF_CH0_NUM_2; in __uniphier_memconf_init()
40 val |= SG_MEMCONF_CH0_SZ_64M; in __uniphier_memconf_init()
43 val |= SG_MEMCONF_CH0_SZ_128M; in __uniphier_memconf_init()
46 val |= SG_MEMCONF_CH0_SZ_256M; in __uniphier_memconf_init()
49 val |= SG_MEMCONF_CH0_SZ_512M; in __uniphier_memconf_init()
52 val |= SG_MEMCONF_CH0_SZ_1G; in __uniphier_memconf_init()
62 val |= SG_MEMCONF_CH1_NUM_1; in __uniphier_memconf_init()
66 val |= SG_MEMCONF_CH1_NUM_2; in __uniphier_memconf_init()
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/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c94 u32 val, mask, tmp; in param_write() local
98 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
100 return regmap_write(base, reg->offset, val); in param_write()
106 u32 mask, val; in rockchip_combphy_is_ready() local
111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
112 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
114 return val; in rockchip_combphy_is_ready()
120 u32 val; in rockchip_combphy_pcie_init() local
131 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
132 val |= BIT(5); in rockchip_combphy_pcie_init()
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H A Dti-pipe3-phy.c110 u32 val; in omap_pipe3_wait_lock() local
115 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS); in omap_pipe3_wait_lock()
116 if (val & PLL_LOCK) in omap_pipe3_wait_lock()
120 if (!(val & PLL_LOCK)) { in omap_pipe3_wait_lock()
130 u32 val; in omap_pipe3_dpll_program() local
139 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
140 val &= ~PLL_REGN_MASK; in omap_pipe3_dpll_program()
141 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
142 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
144 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2); in omap_pipe3_dpll_program()
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/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c38 unsigned int val; in ddr3_mem_ctrl_init() local
52 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
56 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
57 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
60 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
62 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
63 writel(val, &phy1_ctrl->phy_con42); in ddr3_mem_ctrl_init()
90 val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | in ddr3_mem_ctrl_init()
94 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
95 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
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H A Ddmc_common.c22 unsigned long val = 0; in dmc_config_zq() local
30 val = PHY_CON16_RESET_VAL; in dmc_config_zq()
31 val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; in dmc_config_zq()
32 val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; in dmc_config_zq()
33 val |= ZQ_CLK_DIV_EN; in dmc_config_zq()
34 writel(val, phy0_con16); in dmc_config_zq()
35 writel(val, phy1_con16); in dmc_config_zq()
39 val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; in dmc_config_zq()
40 writel(val, phy0_con16); in dmc_config_zq()
41 writel(val, phy1_con16); in dmc_config_zq()
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/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dpinmux-common.c162 u32 val; in pinmux_set_func() local
184 val = readl(reg); in pinmux_set_func()
185 val &= ~(3 << MUX_SHIFT(pin)); in pinmux_set_func()
186 val |= (mux << MUX_SHIFT(pin)); in pinmux_set_func()
187 writel(val, reg); in pinmux_set_func()
193 u32 val; in pinmux_set_pullupdown() local
199 val = readl(reg); in pinmux_set_pullupdown()
200 val &= ~(3 << PULL_SHIFT(pin)); in pinmux_set_pullupdown()
201 val |= (pupd << PULL_SHIFT(pin)); in pinmux_set_pullupdown()
202 writel(val, reg); in pinmux_set_pullupdown()
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/rk3399_rockchip-uboot/drivers/bios_emulator/
H A Dbesys.c143 u8 val = readb_le(BE_memaddr(addr)); in BE_rdb() local
144 return val; in BE_rdb()
165 u16 val = readw_le(base); in BE_rdw() local
166 return val; in BE_rdw()
187 u32 val = readl_le(base); in BE_rdl() local
188 return val; in BE_rdl()
201 void X86API BE_wrb(u32 addr, u8 val) in BE_wrb() argument
204 writeb_le(BE_memaddr(addr), val); in BE_wrb()
217 void X86API BE_wrw(u32 addr, u16 val) in BE_wrw() argument
221 writew_le(base, val); in BE_wrw()
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/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Dti_usb_phy.c136 u32 val; in ti_usb3_dpll_wait_lock() local
138 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_usb3_dpll_wait_lock()
139 if (val & PLL_LOCK) in ti_usb3_dpll_wait_lock()
148 u32 val; in ti_usb3_dpll_program() local
158 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_usb3_dpll_program()
159 val &= ~PLL_REGN_MASK; in ti_usb3_dpll_program()
160 val |= dpll_params->n << PLL_REGN_SHIFT; in ti_usb3_dpll_program()
161 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_usb3_dpll_program()
163 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_usb3_dpll_program()
164 val &= ~PLL_SELFREQDCO_MASK; in ti_usb3_dpll_program()
[all …]
/rk3399_rockchip-uboot/board/qca/ap143/
H A Dap143.c22 u32 val; in board_debug_uart_init() local
30 val = readl(regs + AR71XX_GPIO_REG_OE); in board_debug_uart_init()
31 val |= QCA953X_GPIO(9); in board_debug_uart_init()
32 val &= ~QCA953X_GPIO(10); in board_debug_uart_init()
33 writel(val, regs + AR71XX_GPIO_REG_OE); in board_debug_uart_init()
38 val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); in board_debug_uart_init()
39 val &= ~QCA953X_GPIO_MUX_MASK(16); in board_debug_uart_init()
40 val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; in board_debug_uart_init()
41 writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); in board_debug_uart_init()
46 val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); in board_debug_uart_init()
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/rk3399_rockchip-uboot/include/dt-bindings/pinctrl/
H A Domap.h62 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
63 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
64 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
65 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
66 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
67 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
68 #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
69 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
70 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
78 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) argument
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/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c86 u32 reg, val; in pcc_clock_enable() local
93 val = readl(reg); in pcc_clock_enable()
96 clk, reg, val, enable); in pcc_clock_enable()
98 if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK)) in pcc_clock_enable()
102 val |= PCC_CGC_MASK; in pcc_clock_enable()
104 val &= ~PCC_CGC_MASK; in pcc_clock_enable()
106 writel(val, reg); in pcc_clock_enable()
108 clk_debug("pcc_clock_enable: val 0x%x\n", val); in pcc_clock_enable()
116 u32 reg, val, i, clksrc_type; in pcc_clock_sel() local
142 val = readl(reg); in pcc_clock_sel()
[all …]
/rk3399_rockchip-uboot/board/egnite/ethernut5/
H A Dethernut5_pwrman.c189 int val; in ethernut5_print_celsius() local
192 val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); in ethernut5_print_celsius()
193 val *= 5000; /* 100mV/degree with 5V reference */ in ethernut5_print_celsius()
194 val += 128; /* 8 bit resolution */ in ethernut5_print_celsius()
195 val /= 256; in ethernut5_print_celsius()
196 val -= 450; /* Celsius offset, still x10 */ in ethernut5_print_celsius()
198 printf("%d\n", (val + 5) / 10); in ethernut5_print_celsius()
203 int val; in ethernut5_print_voltage() local
206 val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); in ethernut5_print_voltage()
208 val += 5; in ethernut5_print_voltage()
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/rk3399_rockchip-uboot/include/linux/
H A Diopoll.h28 #define readx_poll_timeout(op, addr, val, cond, timeout_us) \ argument
32 (val) = op(addr); \
36 (val) = op(addr); \
44 #define readb_poll_timeout(addr, val, cond, timeout_us) \ argument
45 readx_poll_timeout(readb, addr, val, cond, timeout_us)
47 #define readw_poll_timeout(addr, val, cond, timeout_us) \ argument
48 readx_poll_timeout(readw, addr, val, cond, timeout_us)
50 #define readl_poll_timeout(addr, val, cond, timeout_us) \ argument
51 readx_poll_timeout(readl, addr, val, cond, timeout_us)
53 #define readq_poll_timeout(addr, val, cond, timeout_us) \ argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h22 #define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSE… argument
31 #define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_O… argument
79 #define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXV… argument
84 #define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_M… argument
89 #define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXV… argument
96 #define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) argument
102 #define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_O… argument
113 #define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) argument
117 #define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) argument
121 #define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) argument
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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Decc.c107 volatile u32 val; in do_ecc() local
141 val = simple_strtoul(argv[2], NULL, 10); in do_ecc()
142 if (val > 255) { in do_ecc()
148 val = (val << ECC_ERROR_MAN_SBEC_SHIFT); in do_ecc()
149 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); in do_ecc()
151 ddr->err_sbe = val; in do_ecc()
154 val = simple_strtoul(argv[2], NULL, 10); in do_ecc()
155 if (val > 255) { in do_ecc()
161 val = (val << ECC_ERROR_MAN_SBET_SHIFT); in do_ecc()
162 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); in do_ecc()
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