Lines Matching refs:val

69 	u32 val;  in omap_usb_dpll_relock()  local
73 val = readl(&phy_regs->pll_status); in omap_usb_dpll_relock()
74 if (val & PLL_LOCK) in omap_usb_dpll_relock()
82 u32 val; in omap_usb_dpll_lock() local
88 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
89 val &= ~PLL_REGN_MASK; in omap_usb_dpll_lock()
90 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_usb_dpll_lock()
91 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
93 val = readl(&phy_regs->pll_config_2); in omap_usb_dpll_lock()
94 val &= ~PLL_SELFREQDCO_MASK; in omap_usb_dpll_lock()
95 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in omap_usb_dpll_lock()
96 writel(val, &phy_regs->pll_config_2); in omap_usb_dpll_lock()
98 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
99 val &= ~PLL_REGM_MASK; in omap_usb_dpll_lock()
100 val |= dpll_params->m << PLL_REGM_SHIFT; in omap_usb_dpll_lock()
101 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
103 val = readl(&phy_regs->pll_config_4); in omap_usb_dpll_lock()
104 val &= ~PLL_REGM_F_MASK; in omap_usb_dpll_lock()
105 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in omap_usb_dpll_lock()
106 writel(val, &phy_regs->pll_config_4); in omap_usb_dpll_lock()
108 val = readl(&phy_regs->pll_config_3); in omap_usb_dpll_lock()
109 val &= ~PLL_SD_MASK; in omap_usb_dpll_lock()
110 val |= dpll_params->sd << PLL_SD_SHIFT; in omap_usb_dpll_lock()
111 writel(val, &phy_regs->pll_config_3); in omap_usb_dpll_lock()
119 u32 val; in usb3_phy_partial_powerup() local
121 val = readl((*ctrl)->control_phy_power_usb); in usb3_phy_partial_powerup()
122 val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); in usb3_phy_partial_powerup()
123 val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); in usb3_phy_partial_powerup()
124 val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; in usb3_phy_partial_powerup()
126 writel(val, (*ctrl)->control_phy_power_usb); in usb3_phy_partial_powerup()
131 u32 val; in usb_phy_power() local
133 val = readl((*ctrl)->control_phy_power_usb); in usb_phy_power()
135 val &= ~USB3_PWRCTL_CLK_CMD_MASK; in usb_phy_power()
136 val |= USB3_PHY_TX_RX_POWERON; in usb_phy_power()
138 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); in usb_phy_power()
141 writel(val, (*ctrl)->control_phy_power_usb); in usb_phy_power()
158 u32 val; in omap_enable_usb3_phy() local
160 val = (USBOTGSS_DMADISABLE | in omap_enable_usb3_phy()
163 writel(val, &omap->otg_wrapper->sysconfig); in omap_enable_usb3_phy()
166 val = readl(&omap->otg_wrapper->utmi_otg_status); in omap_enable_usb3_phy()
167 writel(val, &omap->otg_wrapper->utmi_otg_status); in omap_enable_usb3_phy()
171 val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | in omap_enable_usb3_phy()
180 writel(val, &omap->otg_wrapper->irqenable_set_1); in omap_enable_usb3_phy()
183 val = readl(&omap->otg_wrapper->irqstatus_1); in omap_enable_usb3_phy()
184 writel(val, &omap->otg_wrapper->irqstatus_1); in omap_enable_usb3_phy()
185 val = readl(&omap->otg_wrapper->irqstatus_0); in omap_enable_usb3_phy()
186 writel(val, &omap->otg_wrapper->irqstatus_0); in omap_enable_usb3_phy()
193 u32 reg, val; in omap_enable_usb2_phy2() local
195 val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); in omap_enable_usb2_phy2()
196 writel(val, (*ctrl)->control_srcomp_north_side); in omap_enable_usb2_phy2()
207 val = readl(reg); in omap_enable_usb2_phy2()
208 val |= 0x100; in omap_enable_usb2_phy2()
209 setbits_le32(reg, val); in omap_enable_usb2_phy2()
233 u32 val; in usb_phy_power() local
236 val = readl(USB1_CTRL); in usb_phy_power()
243 val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); in usb_phy_power()
245 val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; in usb_phy_power()
248 writel(val, USB1_CTRL); in usb_phy_power()