110 	u32 val;  in omap_pipe3_wait_lock()  local
115 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in omap_pipe3_wait_lock()
116 		if (val & PLL_LOCK)  in omap_pipe3_wait_lock()
120 	if (!(val & PLL_LOCK)) {  in omap_pipe3_wait_lock()
130 	u32                     val;  in omap_pipe3_dpll_program()  local
139 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
140 	val &= ~PLL_REGN_MASK;  in omap_pipe3_dpll_program()
141 	val |= dpll_params->n << PLL_REGN_SHIFT;  in omap_pipe3_dpll_program()
142 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
144 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in omap_pipe3_dpll_program()
145 	val &= ~PLL_SELFREQDCO_MASK;  in omap_pipe3_dpll_program()
146 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;  in omap_pipe3_dpll_program()
147 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in omap_pipe3_dpll_program()
149 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
150 	val &= ~PLL_REGM_MASK;  in omap_pipe3_dpll_program()
151 	val |= dpll_params->m << PLL_REGM_SHIFT;  in omap_pipe3_dpll_program()
152 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
154 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);  in omap_pipe3_dpll_program()
155 	val &= ~PLL_REGM_F_MASK;  in omap_pipe3_dpll_program()
156 	val |= dpll_params->mf << PLL_REGM_F_SHIFT;  in omap_pipe3_dpll_program()
157 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);  in omap_pipe3_dpll_program()
159 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);  in omap_pipe3_dpll_program()
160 	val &= ~PLL_SD_MASK;  in omap_pipe3_dpll_program()
161 	val |= dpll_params->sd << PLL_SD_SHIFT;  in omap_pipe3_dpll_program()
162 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);  in omap_pipe3_dpll_program()
171 	u32 val, rate;  in omap_control_pipe3_power()  local
173 	val = readl(pipe3->power_reg);  in omap_control_pipe3_power()
179 		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |  in omap_control_pipe3_power()
181 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<  in omap_control_pipe3_power()
183 		val |= rate <<  in omap_control_pipe3_power()
186 		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;  in omap_control_pipe3_power()
187 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<  in omap_control_pipe3_power()
191 	writel(val, pipe3->power_reg);  in omap_control_pipe3_power()
197 	u32 val;  in pipe3_init()  local
201 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_init()
202 	if (!(val & PLL_LOCK)) {  in pipe3_init()
208 		val = omap_pipe3_readl(pipe3->pll_ctrl_base,  in pipe3_init()
210 		if (val & PLL_IDLE) {  in pipe3_init()
211 			val &= ~PLL_IDLE;  in pipe3_init()
213 					  PLL_CONFIGURATION2, val);  in pipe3_init()
244 	u32 val;  in pipe3_exit()  local
251 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in pipe3_exit()
252 	val |= PLL_IDLE;  in pipe3_exit()
253 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in pipe3_exit()
258 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_exit()
259 		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))  in pipe3_exit()
263 	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {  in pipe3_exit()
265 		      __func__, val);  in pipe3_exit()
269 	val = readl(pipe3->pll_reset_reg);  in pipe3_exit()
270 	writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()
272 	writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()