88 	u32 val;  in omap_pipe3_wait_lock()  local
93 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in omap_pipe3_wait_lock()
94 		if (val & PLL_LOCK)  in omap_pipe3_wait_lock()
98 	if (!(val & PLL_LOCK)) {  in omap_pipe3_wait_lock()
108 	u32                     val;  in omap_pipe3_dpll_program()  local
117 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
118 	val &= ~PLL_REGN_MASK;  in omap_pipe3_dpll_program()
119 	val |= dpll_params->n << PLL_REGN_SHIFT;  in omap_pipe3_dpll_program()
120 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
122 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in omap_pipe3_dpll_program()
123 	val &= ~PLL_SELFREQDCO_MASK;  in omap_pipe3_dpll_program()
124 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;  in omap_pipe3_dpll_program()
125 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in omap_pipe3_dpll_program()
127 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
128 	val &= ~PLL_REGM_MASK;  in omap_pipe3_dpll_program()
129 	val |= dpll_params->m << PLL_REGM_SHIFT;  in omap_pipe3_dpll_program()
130 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
132 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);  in omap_pipe3_dpll_program()
133 	val &= ~PLL_REGM_F_MASK;  in omap_pipe3_dpll_program()
134 	val |= dpll_params->mf << PLL_REGM_F_SHIFT;  in omap_pipe3_dpll_program()
135 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);  in omap_pipe3_dpll_program()
137 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);  in omap_pipe3_dpll_program()
138 	val &= ~PLL_SD_MASK;  in omap_pipe3_dpll_program()
139 	val |= dpll_params->sd << PLL_SD_SHIFT;  in omap_pipe3_dpll_program()
140 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);  in omap_pipe3_dpll_program()
149 	u32 val, rate;  in omap_control_phy_power()  local
151 	val = readl(phy->power_reg);  in omap_control_phy_power()
157 		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |  in omap_control_phy_power()
159 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<  in omap_control_phy_power()
161 		val |= rate <<  in omap_control_phy_power()
164 		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;  in omap_control_phy_power()
165 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<  in omap_control_phy_power()
169 	writel(val, phy->power_reg);  in omap_control_phy_power()
175 	u32 val;  in phy_pipe3_power_on()  local
178 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in phy_pipe3_power_on()
179 	if (!(val & PLL_LOCK)) {  in phy_pipe3_power_on()
185 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in phy_pipe3_power_on()
186 		if (val & PLL_IDLE) {  in phy_pipe3_power_on()
187 			val &= ~PLL_IDLE;  in phy_pipe3_power_on()
189 					  PLL_CONFIGURATION2, val);  in phy_pipe3_power_on()
204 	u32 val;  in phy_pipe3_power_off()  local
211 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in phy_pipe3_power_off()
212 	val |= PLL_IDLE;  in phy_pipe3_power_off()
213 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in phy_pipe3_power_off()
218 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in phy_pipe3_power_off()
219 		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))  in phy_pipe3_power_off()
223 	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {  in phy_pipe3_power_off()
225 		       __func__, val);  in phy_pipe3_power_off()