38 	unsigned int val;  in ddr3_mem_ctrl_init()  local
52 	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |  in ddr3_mem_ctrl_init()
56 	writel(val, &phy0_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
57 	writel(val, &phy1_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
60 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |  in ddr3_mem_ctrl_init()
62 	writel(val, &phy0_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
63 	writel(val, &phy1_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
90 	val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |  in ddr3_mem_ctrl_init()
94 	writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
95 	writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
98 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),  in ddr3_mem_ctrl_init()
100 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),  in ddr3_mem_ctrl_init()
140 		val = PHY_CON0_RESET_VAL;  in ddr3_mem_ctrl_init()
141 		val |= P0_CMD_EN;  in ddr3_mem_ctrl_init()
142 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
143 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
145 		val = PHY_CON2_RESET_VAL;  in ddr3_mem_ctrl_init()
146 		val |= INIT_DESKEW_EN;  in ddr3_mem_ctrl_init()
147 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
148 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
150 		val = PHY_CON0_RESET_VAL;  in ddr3_mem_ctrl_init()
151 		val |= P0_CMD_EN;  in ddr3_mem_ctrl_init()
152 		val |= BYTE_RDLVL_EN;  in ddr3_mem_ctrl_init()
153 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
154 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
156 		val = (mem->ctrl_start_point <<  in ddr3_mem_ctrl_init()
162 		writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
163 		writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
165 		val = PHY_CON2_RESET_VAL;  in ddr3_mem_ctrl_init()
166 		val |= INIT_DESKEW_EN;  in ddr3_mem_ctrl_init()
167 		val |= RDLVL_GATE_EN;  in ddr3_mem_ctrl_init()
168 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
169 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
171 		val = PHY_CON0_RESET_VAL;  in ddr3_mem_ctrl_init()
172 		val |= P0_CMD_EN;  in ddr3_mem_ctrl_init()
173 		val |= BYTE_RDLVL_EN;  in ddr3_mem_ctrl_init()
174 		val |= CTRL_SHGATE;  in ddr3_mem_ctrl_init()
175 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
176 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
178 		val = PHY_CON1_RESET_VAL;  in ddr3_mem_ctrl_init()
179 		val &= ~(CTRL_GATEDURADJ_MASK);  in ddr3_mem_ctrl_init()
180 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
181 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
202 		val = (mem->ctrl_start_point <<  in ddr3_mem_ctrl_init()
209 		writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
210 		writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
451 	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;  in ddr3_mem_ctrl_init()  local
485 		val = readl(&clk->mux_stat_cdrex);  in ddr3_mem_ctrl_init()
486 		val &= BPLL_SEL_MASK;  in ddr3_mem_ctrl_init()
487 	} while (val != FOUTBPLL);  in ddr3_mem_ctrl_init()
492 	val = readl(&phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
493 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);  in ddr3_mem_ctrl_init()
494 	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);  in ddr3_mem_ctrl_init()
495 	writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
497 	val = readl(&phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
498 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);  in ddr3_mem_ctrl_init()
499 	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);  in ddr3_mem_ctrl_init()
500 	writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
503 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |  in ddr3_mem_ctrl_init()
505 	writel(val, &phy0_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
506 	writel(val, &phy1_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
508 	val = readl(&phy0_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
509 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);  in ddr3_mem_ctrl_init()
510 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);  in ddr3_mem_ctrl_init()
511 	writel(val, &phy0_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
513 	val = readl(&phy1_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
514 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);  in ddr3_mem_ctrl_init()
515 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);  in ddr3_mem_ctrl_init()
516 	writel(val, &phy1_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
522 	val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |  in ddr3_mem_ctrl_init()
524 	val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |  in ddr3_mem_ctrl_init()
526 	writel(val, &phy0_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
527 	writel(val, &phy1_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
538 	val = readl(&phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
539 	val |= mem->phy0_pulld_dqs;  in ddr3_mem_ctrl_init()
540 	writel(val, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
541 	val = readl(&phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
542 	val |= mem->phy1_pulld_dqs;  in ddr3_mem_ctrl_init()
543 	writel(val, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
545 	val = MEM_TERM_EN | PHY_TERM_EN;  in ddr3_mem_ctrl_init()
546 	writel(val, &drex0->phycontrol0);  in ddr3_mem_ctrl_init()
547 	writel(val, &drex1->phycontrol0);  in ddr3_mem_ctrl_init()
559 		val = readl(&drex0->phystatus);  in ddr3_mem_ctrl_init()
560 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);  in ddr3_mem_ctrl_init()
562 		val = readl(&drex1->phystatus);  in ddr3_mem_ctrl_init()
563 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);  in ddr3_mem_ctrl_init()
577 	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |  in ddr3_mem_ctrl_init()
579 	writel(val, &tzasc0->membaseconfig0);  in ddr3_mem_ctrl_init()
580 	writel(val, &tzasc1->membaseconfig0);  in ddr3_mem_ctrl_init()
583 	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |  in ddr3_mem_ctrl_init()
585 	writel(val, &tzasc0->membaseconfig1);  in ddr3_mem_ctrl_init()
586 	writel(val, &tzasc1->membaseconfig1);  in ddr3_mem_ctrl_init()
638 	val = readl(&clk->gate_bus_cdrex);  in ddr3_mem_ctrl_init()
640 		writel(val & ~0x1, &clk->gate_bus_cdrex);  in ddr3_mem_ctrl_init()
642 		writel(val, &clk->gate_bus_cdrex);  in ddr3_mem_ctrl_init()
650 		writel(val & ~0x2, &clk->gate_bus_cdrex);  in ddr3_mem_ctrl_init()
652 		writel(val, &clk->gate_bus_cdrex);  in ddr3_mem_ctrl_init()
672 			val = readl(&power->pad_retention_dram_status);  in ddr3_mem_ctrl_init()
673 		} while (val != 0x1);  in ddr3_mem_ctrl_init()
698 		val = PHY_CON2_RESET_VAL;  in ddr3_mem_ctrl_init()
699 		val |= INIT_DESKEW_EN;  in ddr3_mem_ctrl_init()
700 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
701 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
703 		val =  readl(&phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
704 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);  in ddr3_mem_ctrl_init()
705 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
707 		val =  readl(&phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
708 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);  in ddr3_mem_ctrl_init()
709 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
723 		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;  in ddr3_mem_ctrl_init()
725 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),  in ddr3_mem_ctrl_init()
727 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),  in ddr3_mem_ctrl_init()
737 		val = readl(&phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
738 		val &= ~(CTRL_GATEDURADJ_MASK);  in ddr3_mem_ctrl_init()
739 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
741 		val = readl(&phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
742 		val &= ~(CTRL_GATEDURADJ_MASK);  in ddr3_mem_ctrl_init()
743 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
778 		val = (0x3 << DIRECT_CMD_BANK_SHIFT);  in ddr3_mem_ctrl_init()
780 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),  in ddr3_mem_ctrl_init()
782 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),  in ddr3_mem_ctrl_init()
787 		val = PHY_CON12_RESET_VAL;  in ddr3_mem_ctrl_init()
788 		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
789 		writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
857 	val = readl(&drex0->concontrol);  in ddr3_mem_ctrl_init()
858 	val |= CONCONTROL_UPDATE_MODE;  in ddr3_mem_ctrl_init()
859 	writel(val, &drex0->concontrol);  in ddr3_mem_ctrl_init()
860 	val = readl(&drex1->concontrol);  in ddr3_mem_ctrl_init()
861 	val |= CONCONTROL_UPDATE_MODE;  in ddr3_mem_ctrl_init()
862 	writel(val, &drex1->concontrol);  in ddr3_mem_ctrl_init()