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Searched refs:regbase (Results 1 – 25 of 27) sorted by relevance

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/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-gpio.c51 static void gpio_bit_op(void __iomem *regbase, unsigned int offset, in gpio_bit_op() argument
54 u32 val = readl(regbase + offset); in gpio_bit_op()
61 writel(val, regbase + offset); in gpio_bit_op()
64 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit) in gpio_bit_rd() argument
66 return readl(regbase + offset) & bit ? 1 : 0; in gpio_bit_rd()
69 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit) in gpio_irq_unmask() argument
71 gpio_bit_op(regbase, GPIO_INTEN, bit, 1); in gpio_irq_unmask()
74 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit) in gpio_irq_mask() argument
76 gpio_bit_op(regbase, GPIO_INTEN, bit, 0); in gpio_irq_mask()
79 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit) in gpio_irq_ack() argument
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H A Dirq-gpio-v2.c54 static void gpio_bit_op(void __iomem *regbase, unsigned int offset, in gpio_bit_op() argument
63 writel(val, regbase + offset); in gpio_bit_op()
66 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit) in gpio_bit_rd() argument
71 return readl(regbase + offset) & bit ? 1 : 0; in gpio_bit_rd()
74 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit) in gpio_irq_unmask() argument
76 gpio_bit_op(regbase, GPIO_INTEN, bit, 1); in gpio_irq_unmask()
79 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit) in gpio_irq_mask() argument
81 gpio_bit_op(regbase, GPIO_INTEN, bit, 0); in gpio_irq_mask()
84 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit) in gpio_irq_ack() argument
86 gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1); in gpio_irq_ack()
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H A Dirq-internal.h60 void __iomem *regbase; member
70 .regbase = (unsigned char __iomem *)GPIO##ID##_PHYS, \
/rk3399_rockchip-uboot/drivers/mmc/
H A Duniphier-sd.c128 void __iomem *regbase; member
160 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_check_error()
198 while (!(readl(priv->regbase + reg) & flag)) { in uniphier_sd_wait_for_irq()
230 writel(0, priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_pio_read_one_block()
234 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_read_one_block()
237 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), in uniphier_sd_pio_read_one_block()
256 writel(0, priv->regbase + UNIPHIER_SD_INFO2); in uniphier_sd_pio_write_one_block()
260 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_write_one_block()
264 priv->regbase + UNIPHIER_SD_BUF); in uniphier_sd_pio_write_one_block()
295 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); in uniphier_sd_dma_start()
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H A Dsti_sdhci.c39 static void sti_mmc_core_config(const u32 regbase, int mmc_instance) in sti_mmc_core_config() argument
51 regbase + FLASHSS_MMC_CORE_CONFIG_1); in sti_mmc_core_config()
55 regbase + FLASHSS_MMC_CORE_CONFIG_2); in sti_mmc_core_config()
57 regbase + FLASHSS_MMC_CORE_CONFIG_3); in sti_mmc_core_config()
60 regbase + FLASHSS_MMC_CORE_CONFIG_2); in sti_mmc_core_config()
62 regbase + FLASHSS_MMC_CORE_CONFIG_3); in sti_mmc_core_config()
65 regbase + FLASHSS_MMC_CORE_CONFIG_4); in sti_mmc_core_config()
H A Dbcmstb_sdhci.c45 int bcmstb_sdhci_init(phys_addr_t regbase) in bcmstb_sdhci_init() argument
57 host->ioaddr = (void *)regbase; in bcmstb_sdhci_init()
H A Dhi6220_dw_mmc.c41 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width) in hi6220_dwmci_add_port() argument
51 host->ioaddr = (void *)(ulong)regbase; in hi6220_dwmci_add_port()
H A Dmv_sdhci.c68 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) in mv_sdh_init() argument
78 host->ioaddr = (void *)regbase; in mv_sdh_init()
89 sdhci_mvebu_mbus_config((void __iomem *)regbase); in mv_sdh_init()
H A Datmel_sdhci.c18 int atmel_sdhci_init(void *regbase, u32 id) in atmel_sdhci_init() argument
30 host->ioaddr = regbase; in atmel_sdhci_init()
H A Ds5p_sdhci.c108 int s5p_sdhci_init(u32 regbase, int index, int bus_width) in s5p_sdhci_init() argument
115 host->ioaddr = (void *)regbase; in s5p_sdhci_init()
/rk3399_rockchip-uboot/drivers/ata/
H A Dsata_mv.c255 u32 regbase; member
288 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); in mv_stop_edma_engine()
292 u32 reg = in_le32(priv->regbase + EDMA_CMD); in mv_stop_edma_engine()
309 tmp = in_le32(priv->regbase + SIR_SSTATUS); in mv_start_edma_engine()
315 tmp = in_le32(priv->regbase + PIO_CMD_STATUS); in mv_start_edma_engine()
322 out_le32(priv->regbase + EDMA_IECR, 0x0); in mv_start_edma_engine()
329 tmp = in_le32(priv->regbase + EDMA_CFG); in mv_start_edma_engine()
332 out_le32(priv->regbase + EDMA_CFG, tmp); in mv_start_edma_engine()
334 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); in mv_start_edma_engine()
337 out_le32(priv->regbase + SIR_FIS_CFG, 0x0); in mv_start_edma_engine()
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/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi_apb.c380 cadence_qspi_apb_controller_disable(plat->regbase); in cadence_qspi_apb_controller_init()
383 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
389 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
392 writel(0, plat->regbase + CQSPI_REG_REMAP); in cadence_qspi_apb_controller_init()
395 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION); in cadence_qspi_apb_controller_init()
398 writel(0, plat->regbase + CQSPI_REG_IRQMASK); in cadence_qspi_apb_controller_init()
400 cadence_qspi_apb_controller_enable(plat->regbase); in cadence_qspi_apb_controller_init()
556 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); in cadence_qspi_apb_indirect_read_setup()
567 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); in cadence_qspi_apb_indirect_read_setup()
577 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); in cadence_qspi_apb_indirect_read_setup()
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H A Dcadence_qspi.c28 cadence_qspi_apb_config_baudrate_div(priv->regbase, in cadence_spi_write_speed()
32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
43 void *base = priv->regbase; in spi_calibration()
129 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_speed()
147 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_speed()
159 priv->regbase = plat->regbase; in cadence_spi_probe()
175 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_mode()
178 cadence_qspi_apb_set_clk_mode(priv->regbase, mode); in cadence_spi_set_mode()
181 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_mode()
193 void *base = priv->regbase; in cadence_spi_xfer()
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H A Drockchip_sfc.c183 void __iomem *regbase; member
210 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); in rockchip_sfc_reset()
212 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, in rockchip_sfc_reset()
219 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_reset()
228 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); in rockchip_sfc_get_version()
263 writel(val, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_DLL_CTRL0); in rockchip_sfc_set_delay_lines()
289 printf("sfc cmd=%02xH(6BH-x4)\n", readl(sfc->regbase + SFC_CMD) & 0xFF); in rockchip_sfc_init()
291 writel(0, sfc->regbase + SFC_CTRL); in rockchip_sfc_init()
293 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); in rockchip_sfc_init()
295 reg = readl(sfc->regbase + SFC_EXT_CTRL); in rockchip_sfc_init()
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H A Dcadence_qspi.h19 void *regbase; member
36 void *regbase; member
/rk3399_rockchip-uboot/drivers/sound/
H A Drockchip-i2s.c18 void *regbase; member
24 return readl(dev->regbase + offset); in i2s_reg_readl()
29 writel(val, dev->regbase + offset); in i2s_reg_writel()
37 orig = readl(dev->regbase + offset); in i2s_reg_update_bits()
43 writel(tmp, dev->regbase + offset); in i2s_reg_update_bits()
51 debug("0x%02x: 0x%08x\n", i, readl(dev->regbase + i)); in dump_regs()
152 i2s->regbase = dev_read_addr_ptr(dev); in rockchip_i2s_probe()
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dvf610_nfc.c243 static inline void vf610_nfc_clear_status(void __iomem *regbase) in vf610_nfc_clear_status() argument
245 void __iomem *reg = regbase + NFC_IRQ_STATUS; in vf610_nfc_clear_status()
298 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, in vf610_nfc_send_command() argument
301 void __iomem *reg = regbase + NFC_FLASH_CMD2; in vf610_nfc_send_command()
303 vf610_nfc_clear_status(regbase); in vf610_nfc_send_command()
313 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, in vf610_nfc_send_commands() argument
316 void __iomem *reg = regbase + NFC_FLASH_CMD1; in vf610_nfc_send_commands()
318 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); in vf610_nfc_send_commands()
347 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) in vf610_nfc_transfer_size() argument
349 __raw_writel(size, regbase + NFC_SECTOR_SIZE); in vf610_nfc_transfer_size()
/rk3399_rockchip-uboot/arch/arm/mach-bcmstb/include/mach/
H A Dsdhci.h13 int bcmstb_sdhci_init(phys_addr_t regbase);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-hi6220/
H A Ddwmmc.h8 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Datmel_sdhci.h11 int atmel_sdhci_init(void *regbase, u32 id);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-hi3798cv200/
H A Ddwmmc.h11 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
/rk3399_rockchip-uboot/arch/arm/mach-bcm283x/include/mach/
H A Dsdhci.h16 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/
H A Dmmc.h56 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dmmc.h58 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-meson/
H A Dsd_emmc.h85 void *regbase; member

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