spi: rockchip_sfc: Support auto_merge

Change-Id: I4416b004d315f2f5689312b1eb53e36fce7f6bbf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support maximum dll cell setting for chips

Change-Id: I4349832bd5ba07ae1aed6df27c1c2ab39b93137e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support sclk_x2_bypass

Change-Id: I1f2af9c75389bafa530b2a48b32cbb765973e4d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: spi-rockchip-sfc: Support SFC_VER_9

Change-Id: Id1bd812f400a9be437c3824c7c19f90dbae81783
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Print Bootrom cmd info

6BH means quad line, 03H means single line.

Change-Id: I9082528be43039383e0e732bc80285d05c6ed15b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support sclk_x2 version

SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.

Change-Id: I38e17cf1c33b4a4bdcc0a24a91bd7359512a144a
Signed

spi: rockchip_sfc: Support sclk_x2 version

SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.

Change-Id: I38e17cf1c33b4a4bdcc0a24a91bd7359512a144a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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spi: rockchip_sfc: Support cs-gpios

Change-Id: Ida79e915a84081bf58b36978c0c4351927aba380
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Initial the version at the first

Change-Id: I353d581c11daf6b15b48e44e61cbd2985d6387b3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support tx fifo 128B

Change-Id: If2bb5eee2a2db27191e09254bf0543d62b31fc40
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Add macro limitation for dll tuning apis

Change-Id: I54d41c2f6a138f92a6470d80a5b9d3c00070136e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support chip select 1

Change-Id: I13b4769eb0c8a2414a0c9b7cd35cae35d09f3dd0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support ver8

Change-Id: I2733ae03f25c715771c624e0e78a11f1b07c3440
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Remove useless cache flush for SPI_DMA_PREPARE read

Change-Id: I63185ee05e893b64672223a48ee778f86a620fc8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support ver6

Change-Id: I16b8796e61eb34de727cf1d34a32ac64ac11c0f9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support delay line tuning

Change-Id: I38b26cf15e0c82c713245defaf2478a9708e3f92
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Supoprt spi async transfer

Change-Id: Ib7e09ea564db0d673effab506a90c7cb9fbb4a33
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: spi: rockchip_sfc: Using read_poll

Using read_poll logic.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: I5e24cd0930f299117d7f34af7275f5fbe5f48a95
Signed-off-by: Jon Lin <jo

UPSTREAM: spi: rockchip_sfc: Using read_poll

Using read_poll logic.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: I5e24cd0930f299117d7f34af7275f5fbe5f48a95
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from 20210819094557.v2.2.Ie019ef3e204a0095d9580fa48b7cbf9b9e05fc33@changeid)

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UPSTREAM: spi: rockchip_sfc: Implement set_speed logic

Set clock related processing into set_speed logic. And Optimize
printing format.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id:

UPSTREAM: spi: rockchip_sfc: Implement set_speed logic

Set clock related processing into set_speed logic. And Optimize
printing format.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: Iaf6f3d58cc44deb4a22d74984531b32c53386201
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from 20210819094557.v2.1.Id0647655ab4060f95c9a49fe834465bbe39b8d31@changeid)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: spi: rockchip_sfc: add support for Rockchip SFC

This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, howev

UPSTREAM: spi: rockchip_sfc: add support for Rockchip SFC

This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.

This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3fb08a21387b9f4f24cfd5b45f9d7f344d40fba4)
Change-Id: I75e1fcae03c060c2b8ccf8c49e026dc882469166

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spi: rockchip_sfc: Ajudst the dll strategy

1.max_dll_cells is 0x1FF when sfc_ver_4
2.sfc_set_delay_lines to zero means disable dll
3.bypass dll training when there is no device
4.Adjust the dll_valu

spi: rockchip_sfc: Ajudst the dll strategy

1.max_dll_cells is 0x1FF when sfc_ver_4
2.sfc_set_delay_lines to zero means disable dll
3.bypass dll training when there is no device
4.Adjust the dll_value to from the middle of the dll window to
the better one
5.Change RKSFC_DLL_THRESHOLD_RATE to ">50MHz"

Change-Id: I53812e2865b14506b3cdbfb510d71a633b99c768
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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spi: rockchip_sfc: Optimization method of DLL tuning

According to the actual test window is usually large and in the
middle.

Change-Id: I77ba78276c021efbe1cd56c26f17b49abc6ac073
Signed-off-by: Jon

spi: rockchip_sfc: Optimization method of DLL tuning

According to the actual test window is usually large and in the
middle.

Change-Id: I77ba78276c021efbe1cd56c26f17b49abc6ac073
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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spi: rockchip_sfc: Support DLL tuning

1.Support after SFC ver 4
2.If the io rate is high than 100MHz, enable SFC delay line in
default
3.Get id byte as data pattern

Change-Id: Id112ec3ae943b6fd131a

spi: rockchip_sfc: Support DLL tuning

1.Support after SFC ver 4
2.If the io rate is high than 100MHz, enable SFC delay line in
default
3.Get id byte as data pattern

Change-Id: Id112ec3ae943b6fd131abe56abc508b358a7416f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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spi: rockchip_sfc: set clock depended on CONFIG_IS_ENABLED(CLK)

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Icb3662d97eeea8db1e1a62f633f9ba4de9b72dde

spi: rockchip_sfc: Limit io rate to 100MHz

Change-Id: Icec10dbe65d5bbef72b858447aa15e848084712b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support dma xfer prepare

Change-Id: I9c3285daf22775fa3ad72e41abcd205c4caaaaa4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>