1*f36ea2f6SThomas Fitzsimmons // SPDX-License-Identifier: GPL-2.0+
2*f36ea2f6SThomas Fitzsimmons /*
3*f36ea2f6SThomas Fitzsimmons * (C) Copyright 2018 Cisco Systems, Inc.
4*f36ea2f6SThomas Fitzsimmons *
5*f36ea2f6SThomas Fitzsimmons * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
6*f36ea2f6SThomas Fitzsimmons */
7*f36ea2f6SThomas Fitzsimmons
8*f36ea2f6SThomas Fitzsimmons #include <common.h>
9*f36ea2f6SThomas Fitzsimmons #include <mach/sdhci.h>
10*f36ea2f6SThomas Fitzsimmons #include <malloc.h>
11*f36ea2f6SThomas Fitzsimmons #include <sdhci.h>
12*f36ea2f6SThomas Fitzsimmons
13*f36ea2f6SThomas Fitzsimmons /*
14*f36ea2f6SThomas Fitzsimmons * The BCMSTB SDHCI has a quirk in that its actual maximum frequency
15*f36ea2f6SThomas Fitzsimmons * capability is 100 MHz. The divisor that is eventually written to
16*f36ea2f6SThomas Fitzsimmons * SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
17*f36ea2f6SThomas Fitzsimmons * reports, and relative to this maximum frequency.
18*f36ea2f6SThomas Fitzsimmons *
19*f36ea2f6SThomas Fitzsimmons * This define used to be set to 52000000 (52 MHz), the desired
20*f36ea2f6SThomas Fitzsimmons * maximum frequency, but that would result in the communication
21*f36ea2f6SThomas Fitzsimmons * actually running at 100 MHz (seemingly without issue), which is
22*f36ea2f6SThomas Fitzsimmons * out-of-spec.
23*f36ea2f6SThomas Fitzsimmons *
24*f36ea2f6SThomas Fitzsimmons * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
25*f36ea2f6SThomas Fitzsimmons * the capabilities register, and the resulting divisor will be
26*f36ea2f6SThomas Fitzsimmons * doubled, meaning that the clock control register will be set to the
27*f36ea2f6SThomas Fitzsimmons * in-spec 52 MHz value.
28*f36ea2f6SThomas Fitzsimmons */
29*f36ea2f6SThomas Fitzsimmons #define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
30*f36ea2f6SThomas Fitzsimmons /*
31*f36ea2f6SThomas Fitzsimmons * When the minimum clock frequency is set to 0 (auto-detect), U-Boot
32*f36ea2f6SThomas Fitzsimmons * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
33*f36ea2f6SThomas Fitzsimmons * which results in the controller timing out when trying to
34*f36ea2f6SThomas Fitzsimmons * communicate with the MMC device. Hard-code this value to 400000
35*f36ea2f6SThomas Fitzsimmons * (400 kHz) to prevent this.
36*f36ea2f6SThomas Fitzsimmons */
37*f36ea2f6SThomas Fitzsimmons #define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
38*f36ea2f6SThomas Fitzsimmons
39*f36ea2f6SThomas Fitzsimmons static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
40*f36ea2f6SThomas Fitzsimmons
41*f36ea2f6SThomas Fitzsimmons /*
42*f36ea2f6SThomas Fitzsimmons * This driver has only been tested with eMMC devices; SD devices may
43*f36ea2f6SThomas Fitzsimmons * not work.
44*f36ea2f6SThomas Fitzsimmons */
bcmstb_sdhci_init(phys_addr_t regbase)45*f36ea2f6SThomas Fitzsimmons int bcmstb_sdhci_init(phys_addr_t regbase)
46*f36ea2f6SThomas Fitzsimmons {
47*f36ea2f6SThomas Fitzsimmons struct sdhci_host *host = NULL;
48*f36ea2f6SThomas Fitzsimmons
49*f36ea2f6SThomas Fitzsimmons host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
50*f36ea2f6SThomas Fitzsimmons if (!host) {
51*f36ea2f6SThomas Fitzsimmons printf("%s: Failed to allocate memory\n", __func__);
52*f36ea2f6SThomas Fitzsimmons return 1;
53*f36ea2f6SThomas Fitzsimmons }
54*f36ea2f6SThomas Fitzsimmons memset(host, 0, sizeof(*host));
55*f36ea2f6SThomas Fitzsimmons
56*f36ea2f6SThomas Fitzsimmons host->name = BCMSTB_SDHCI_NAME;
57*f36ea2f6SThomas Fitzsimmons host->ioaddr = (void *)regbase;
58*f36ea2f6SThomas Fitzsimmons host->quirks = 0;
59*f36ea2f6SThomas Fitzsimmons
60*f36ea2f6SThomas Fitzsimmons host->cfg.part_type = PART_TYPE_DOS;
61*f36ea2f6SThomas Fitzsimmons
62*f36ea2f6SThomas Fitzsimmons host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
63*f36ea2f6SThomas Fitzsimmons
64*f36ea2f6SThomas Fitzsimmons return add_sdhci(host,
65*f36ea2f6SThomas Fitzsimmons BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
66*f36ea2f6SThomas Fitzsimmons BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
67*f36ea2f6SThomas Fitzsimmons }
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