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Searched refs:reg_read (Results 1 – 25 of 33) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
149 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
183 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_high_2_low()
188 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR); in ddr3_dfs_high_2_low()
198 reg = reg_read(REG_DDR3_MR1_CS_ADDR + in ddr3_dfs_high_2_low()
207 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
213 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_high_2_low()
220 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_write_leveling.c76 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
90 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
96 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_write_leveling_hw()
100 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw()
163 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR) | in ddr3_write_leveling_hw()
219 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_wl_supplement()
252 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
401 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
451 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_wl_supplement()
456 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_wl_supplement()
[all …]
H A Dddr3_init.c72 printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); in debug_print_reg()
227 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
378 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init_main()
395 reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25)); in ddr3_init_main()
453 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init_main()
474 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
496 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
513 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init_main()
539 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & in ddr3_init_main()
572 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); in ddr3_init_main()
[all …]
H A Dddr3_hw_training.c106 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
115 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
124 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
130 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
132 reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2; in ddr3_hw_training()
140 reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
142 reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
171 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS)) in ddr3_hw_training()
519 reg = reg_read(REG_SDRAM_TIMING_HIGH_ADDR); in ddr3_set_performance_params()
568 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_write_pup_reg()
[all …]
H A Dddr3_read_leveling.c79 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_read_leveling_hw()
85 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
90 if (reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
152 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) & in ddr3_read_leveling_hw()
155 reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR) & in ddr3_read_leveling_hw()
189 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
208 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
220 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_sw()
228 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_sw()
299 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
[all …]
H A Dxor.c28 xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
30 xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
32 xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
146 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
172 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
262 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
352 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
H A Dddr3_pbs.c109 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_tx()
160 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
286 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
382 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_tx()
387 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_pbs_tx()
552 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_rx()
602 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_rx()
674 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
680 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_rx()
688 reg = (reg_read(REG_DRAM_TRAINING_2_ADDR)) in ddr3_pbs_rx()
[all …]
H A Dddr3_sdram.c54 while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) & in xor_waiton_eng()
565 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) & in ddr3_flush_l1_line()
642 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
649 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_reset_phy_read_fifo()
658 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_reset_phy_read_fifo()
662 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
H A Dddr3_dqs.c139 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_rx()
159 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
188 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
194 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_rx()
199 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_rx()
221 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_tx()
239 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
268 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
274 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_tx()
279 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_tx()
H A Dddr3_spd.c691 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
698 reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
891 reg |= (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) & 0xF0FFFF);
964 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
998 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1005 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1084 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
1198 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR);
1207 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
1231 reg = reg_read(REG_SDRAM_OPERATION_ADDR) &
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.c45 tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); in hws_pex_config()
51 tmp = reg_read(SOC_CTRL_REG); in hws_pex_config()
113 tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); in hws_pex_config()
124 temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS in hws_pex_config()
130 temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( in hws_pex_config()
172 tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); in hws_pex_config()
180 tmp = reg_read(PEX_CTRL_REG(pex_idx)); in hws_pex_config()
216 dev_id = reg_read(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
240 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_bus_num_set()
255 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_dev_num_set()
[all …]
H A Dsys_env_lib.c63 value = (reg_read(DEVICE_SAMPLE_AT_RESET1_REG) >> 15) & 0x1; in mv_board_tclk_get()
124 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
130 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
138 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
194 u32 default_ctrl_id, ctrl_id = reg_read(DEV_ID_REG); in sys_env_model_get()
232 g_dev_id = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in sys_env_device_id_get()
H A Dseq_exec.c55 reg_data = reg_read(reg_addr); in write_op_execute()
114 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c143 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) in board_modules_scan()
175 sar = reg_read(MPP_SAMPLE_AT_RESET(0)); in board_cpu_freq_get()
176 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1)); in board_cpu_freq_get()
285 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in serdes_phy_config()
305 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG); in serdes_phy_config()
312 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); in serdes_phy_config()
320 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) & in serdes_phy_config()
325 core_avs = reg_read(CORE_AVS_CONTROL_0REG); in serdes_phy_config()
337 core_avs = reg_read(CORE_AVS_CONTROL_2REG); in serdes_phy_config()
343 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_phy_config()
[all …]
/rk3399_rockchip-uboot/board/micronas/vct/
H A Dtop.c39 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); in top_read_pin()
42 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); in top_read_pin()
45 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); in top_read_pin()
48 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); in top_read_pin()
57 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_read_pin()
61 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
131 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_set_pin()
H A Ddcgu.c35 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); in dcgu_set_clk_switch()
37 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
121 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); in dcgu_set_clk_switch()
124 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
148 val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); in dcgu_set_reset_switch()
H A Dgpio.c37 reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); in clrsetbits()
72 value = reg_read(GPIO_EXT_PORTA(gpio_base)); in vct_gpio_get()
H A Dehci.c28 val = reg_read(addr); in vct_ehci_hcd_init()
30 val = reg_read(addr); in vct_ehci_hcd_init()
H A Debi_smc911x.c45 data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); in smc911x_reg_read()
83 data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); in pkt_data_pull()
H A Debi_nor_flash.c18 return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); in ebi_read()
36 while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { in ebi_write_u16()
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c131 value = reg_read(DEV_VERSION_ID_REG); in sys_env_device_rev_get()
174 return reg_read(REG_DDR3_RANK_CTRL_ADDR) & in sys_env_get_cs_ena_from_reg()
240 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
304 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init()
332 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init()
343 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init()
405 reg = reg_read(REG_BOOTROM_ROUTINE_ADDR); in ddr3_init()
461 reg = reg_read(reg_addr); in ddr3_get_static_mc_value()
573 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); in ddr3_new_tip_dlb_config()
664 bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >> in ddr3_get_bus_width()
[all …]
H A Dxor.c32 ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
35 reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
38 reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
148 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
174 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
242 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
H A Dddr3_a38x.c209 if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0) in ddr3_ctrl_get_junc_temp()
214 if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) { in ddr3_ctrl_get_junc_temp()
219 reg = reg_read(TSEN_STATUS_REG); in ddr3_ctrl_get_junc_temp()
313 *data = reg_read(reg_addr) & mask; in ddr3_tip_a38x_if_read()
330 reg = reg_read(CS_ENABLE_REG); in ddr3_tip_a38x_select_ddr_controller()
483 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_init_freq()
534 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_medium_freq()
602 sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_set_divider()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A Ddram.c122 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, in mv_xor_init2()
124 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, in mv_xor_init2()
126 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, in mv_xor_init2()
177 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
207 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
214 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()
/rk3399_rockchip-uboot/drivers/spi/
H A Dmxc_spi.c35 #define reg_read readl macro
187 reg_config = reg_read(&regs->cfg); in spi_cfg_mxc()
288 status = reg_read(&regs->stat); in spi_xchg_single()
295 status = reg_read(&regs->stat); in spi_xchg_single()
306 data = reg_read(&regs->rxdata); in spi_xchg_single()
319 tmp = reg_read(&regs->rxdata); in spi_xchg_single()

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