72 	printf("0x%08x = 0x%08x\n", reg, reg_read(reg));  in debug_print_reg()
227 		win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);  in ddr3_save_and_set_training_windows()
378 	soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>  in ddr3_init_main()
395 	reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));  in ddr3_init_main()
453 	if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &  in ddr3_init_main()
474 		reg = reg_read(REG_SDRAM_CONFIG_ADDR);  in ddr3_init_main()
496 	reg = reg_read(REG_SDRAM_CONFIG_ADDR);  in ddr3_init_main()
513 	reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);  in ddr3_init_main()
539 	if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &  in ddr3_init_main()
572 		reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);  in ddr3_init_main()
593 		reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &  in ddr3_init_main()
623 		reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &  in ddr3_init_main()
644 	reg = reg_read(REG_SDRAM_CONFIG_ADDR) &  in ddr3_init_main()
655 	reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);  in ddr3_init_main()
662 		reg = reg_read(REG_SDRAM_CONFIG_ADDR);  in ddr3_init_main()
670 	reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);  in ddr3_init_main()
699 	reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);	/* 0xE8200 */  in ddr3_get_cpu_freq()
704 	reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);	/* 0x18230 [23:21] */  in ddr3_get_cpu_freq()
708 	reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);	/* 0x18234 [20] */  in ddr3_get_cpu_freq()
734 	reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);  in ddr3_get_fab_opt()
739 	reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);  in ddr3_get_fab_opt()
798 				reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &  in ddr3_static_training_init()
821 	reg = reg_read(reg_addr);  in ddr3_get_static_mc_value()
895 				reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &  in ddr3_static_mc_init()
1094 	return reg_read(REG_DDR3_RANK_CTRL_ADDR) &  in ddr3_get_cs_ena_from_reg()
1127 	rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,  in mv_ctrl_rev_get()