Home
last modified time | relevance | path

Searched refs:phy_write (Results 1 – 25 of 51) sorted by relevance

123

/rk3399_rockchip-uboot/drivers/net/phy/
H A Drk630phy.c139 phy_write(phydev, 0, MDIO_DEVAD_NONE, in rk630_phy_s40_config_init()
143 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100); in rk630_phy_s40_config_init()
145 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824); in rk630_phy_s40_config_init()
147 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200); in rk630_phy_s40_config_init()
149 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE2_AFE_CTRL, 0x0000); in rk630_phy_s40_config_init()
151 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0600); in rk630_phy_s40_config_init()
153 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_TX_CTRL, 0x708f); in rk630_phy_s40_config_init()
155 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_RX_CTRL, 0xf000); in rk630_phy_s40_config_init()
156 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_DRIVER2, 0x1530); in rk630_phy_s40_config_init()
159 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800); in rk630_phy_s40_config_init()
[all …]
H A Dmarvell.c111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
216 phy_write(phydev, in m88e1111s_config()
229 phy_write(phydev, in m88e1111s_config()
241 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
[all …]
H A Datheros.c22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
41 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
43 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
63 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); in ar8035_config()
[all …]
H A Dvitesse.c73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
125 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
131 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
135 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
154 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
174 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
181 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8574_config()
184 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, in vsc8574_config()
189 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); in vsc8574_config()
[all …]
H A Dbroadcom.c43 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
53 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
140 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
143 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5482_config()
147 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); in bcm5482_config()
150 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5482_config()
153 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, in bcm5482_config()
155 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, in bcm5482_config()
[all …]
H A Dmscc.c142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
174 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
182 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
188 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
[all …]
H A Dti.c122 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
125 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
128 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
155 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
158 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
161 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
164 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
233 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
237 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
243 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, in dp83867_config()
[all …]
H A Drealtek.c66 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
71 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
82 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg); in rtl8211f_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f); in rtl8211f_config()
118 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
[all …]
H A Dmicrel_ksz90x1.c222 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
224 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
270 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
295 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
298 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
301 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
304 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
311 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
313 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
[all …]
H A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
H A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
H A Drockchip-fephy.c67 ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_READ(group, reg)); in rockchip_fephy_group_read()
83 ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTWRITE, val); in rockchip_fephy_group_write()
87 return phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_WRITE(group, reg)); in rockchip_fephy_group_write()
110 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_LED_CTRL, 0x7aa); in rockchip_fephy_config_init()
H A Dteranetics.c33 phy_write(phydev, 30, 93, 2); in tn2020_config()
34 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); in tn2020_config()
36 phy_write(phydev, 30, 93, 1); in tn2020_config()
H A Daquantia.c32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
48 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); in aquantia_config()
49 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); in aquantia_config()
56 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dsamsung_mipi_dcphy.c1236 phy_write(struct samsung_mipi_dcphy *samsung, u32 reg, u32 val) in phy_write() function
1254 phy_write(samsung, reg, tmp); in phy_update_bits()
1307 phy_write(samsung, BIAS_CON0, 0x0010); in samsung_mipi_dcphy_bias_block_enable()
1308 phy_write(samsung, BIAS_CON1, 0x0110); in samsung_mipi_dcphy_bias_block_enable()
1309 phy_write(samsung, BIAS_CON2, 0x3223); in samsung_mipi_dcphy_bias_block_enable()
1323 phy_write(samsung, PLL_CON1, samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1327 phy_write(samsung, PLL_CON3, in samsung_mipi_dcphy_pll_configure()
1332 phy_write(samsung, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL); in samsung_mipi_dcphy_pll_configure()
1333 phy_write(samsung, PLL_CON7, PLL_LOCK_CNT(0xf000)); in samsung_mipi_dcphy_pll_configure()
1334 phy_write(samsung, PLL_CON8, PLL_STB_CNT(0xf000)); in samsung_mipi_dcphy_pll_configure()
[all …]
/rk3399_rockchip-uboot/board/spear/x600/
H A Dx600.c84 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
121 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
124 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
127 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
130 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/rk3399_rockchip-uboot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c96 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/rk3399_rockchip-uboot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
343 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
344 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG); in mx6_rgmii_rework()
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6); in mx6_rgmii_rework()
[all …]
/rk3399_rockchip-uboot/board/keymile/kmp204x/
H A Deth.c64 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); in board_phy_config()
65 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); in board_phy_config()
66 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); in board_phy_config()
/rk3399_rockchip-uboot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c193 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in board_phy_config()
194 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in board_phy_config()
195 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in board_phy_config()
200 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in board_phy_config()
203 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in board_phy_config()
206 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in board_phy_config()
/rk3399_rockchip-uboot/board/gdsys/a38x/
H A Dihs_phys.c32 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004); in ihs_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); in ihs_phy_config()
47 phy_write(phydev, MDIO_DEVAD_NONE, 26, reg); in ihs_phy_config()
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in ihs_phy_config()
53 phy_write(phydev, MDIO_DEVAD_NONE, 4, reg); in ihs_phy_config()
56 phy_write(phydev, MDIO_DEVAD_NONE, 9, reg); in ihs_phy_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); in ihs_phy_config()
/rk3399_rockchip-uboot/include/
H A Dphy.h169 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, in phy_write() function
181 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); in phy_mmd_start_indirect()
184 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); in phy_mmd_start_indirect()
187 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, in phy_mmd_start_indirect()
230 return phy_write(phydev, devad, regnum, val); in phy_write_mmd()
236 return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); in phy_write_mmd()
/rk3399_rockchip-uboot/board/tbs/tbs2910/
H A Dtbs2910.c367 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8035_phy_fixup()
368 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_phy_fixup()
369 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_phy_fixup()
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8035_phy_fixup()
377 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8035_phy_fixup()
380 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8035_phy_fixup()
/rk3399_rockchip-uboot/board/wandboard/
H A Dwandboard.c197 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
198 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
199 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
204 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
207 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
210 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/rk3399_rockchip-uboot/board/compulab/cm_fx6/
H A Dcm_fx6.c414 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in mx6_rgmii_rework()
415 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in mx6_rgmii_rework()
416 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in mx6_rgmii_rework()
419 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
422 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in mx6_rgmii_rework()
423 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in mx6_rgmii_rework()
424 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in mx6_rgmii_rework()
429 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
432 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in mx6_rgmii_rework()
435 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in mx6_rgmii_rework()

123