1*877bfe37SValentin Longchamp /*
2*877bfe37SValentin Longchamp * (C) Copyright 2013 Keymile AG
3*877bfe37SValentin Longchamp * Valentin Longchamp <valentin.longchamp@keymile.com>
4*877bfe37SValentin Longchamp *
5*877bfe37SValentin Longchamp * SPDX-License-Identifier: GPL-2.0+
6*877bfe37SValentin Longchamp */
7*877bfe37SValentin Longchamp
8*877bfe37SValentin Longchamp #include <common.h>
9*877bfe37SValentin Longchamp #include <netdev.h>
10*877bfe37SValentin Longchamp #include <fm_eth.h>
11*877bfe37SValentin Longchamp #include <fsl_mdio.h>
12*877bfe37SValentin Longchamp #include <phy.h>
13*877bfe37SValentin Longchamp
board_eth_init(bd_t * bis)14*877bfe37SValentin Longchamp int board_eth_init(bd_t *bis)
15*877bfe37SValentin Longchamp {
16*877bfe37SValentin Longchamp int ret = 0;
17*877bfe37SValentin Longchamp #ifdef CONFIG_FMAN_ENET
18*877bfe37SValentin Longchamp struct fsl_pq_mdio_info dtsec_mdio_info;
19*877bfe37SValentin Longchamp
20*877bfe37SValentin Longchamp printf("Initializing Fman\n");
21*877bfe37SValentin Longchamp
22*877bfe37SValentin Longchamp dtsec_mdio_info.regs =
23*877bfe37SValentin Longchamp (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
24*877bfe37SValentin Longchamp dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
25*877bfe37SValentin Longchamp
26*877bfe37SValentin Longchamp /* Register the real 1G MDIO bus */
27*877bfe37SValentin Longchamp fsl_pq_mdio_init(bis, &dtsec_mdio_info);
28*877bfe37SValentin Longchamp
29*877bfe37SValentin Longchamp /* DTESC1/2 don't have a PHY, they are temporarily disabled
30*877bfe37SValentin Longchamp * so that u-boot doesn't try to unsuccessfuly enable them */
31*877bfe37SValentin Longchamp fm_disable_port(FM1_DTSEC1);
32*877bfe37SValentin Longchamp fm_disable_port(FM1_DTSEC2);
33*877bfe37SValentin Longchamp
34*877bfe37SValentin Longchamp /*
35*877bfe37SValentin Longchamp * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
36*877bfe37SValentin Longchamp * This is the debug interface, the only one used in u-boot
37*877bfe37SValentin Longchamp */
38*877bfe37SValentin Longchamp fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
39*877bfe37SValentin Longchamp fm_info_set_mdio(FM1_DTSEC5,
40*877bfe37SValentin Longchamp miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
41*877bfe37SValentin Longchamp
42*877bfe37SValentin Longchamp ret = cpu_eth_init(bis);
43*877bfe37SValentin Longchamp
44*877bfe37SValentin Longchamp /* reenable DTSEC1/2 for later (kernel) */
45*877bfe37SValentin Longchamp fm_enable_port(FM1_DTSEC1);
46*877bfe37SValentin Longchamp fm_enable_port(FM1_DTSEC2);
47*877bfe37SValentin Longchamp #endif
48*877bfe37SValentin Longchamp
49*877bfe37SValentin Longchamp return ret;
50*877bfe37SValentin Longchamp }
51*877bfe37SValentin Longchamp
52*877bfe37SValentin Longchamp #if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
53*877bfe37SValentin Longchamp
54*877bfe37SValentin Longchamp #define mv88E1118_PAGE_REG 22
55*877bfe37SValentin Longchamp
board_phy_config(struct phy_device * phydev)56*877bfe37SValentin Longchamp int board_phy_config(struct phy_device *phydev)
57*877bfe37SValentin Longchamp {
58*877bfe37SValentin Longchamp if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
59*877bfe37SValentin Longchamp /* driver config is good */
60*877bfe37SValentin Longchamp if (phydev->drv->config)
61*877bfe37SValentin Longchamp phydev->drv->config(phydev);
62*877bfe37SValentin Longchamp
63*877bfe37SValentin Longchamp /* but we still need to fix the LEDs */
64*877bfe37SValentin Longchamp phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
65*877bfe37SValentin Longchamp phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
66*877bfe37SValentin Longchamp phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
67*877bfe37SValentin Longchamp }
68*877bfe37SValentin Longchamp
69*877bfe37SValentin Longchamp return 0;
70*877bfe37SValentin Longchamp }
71*877bfe37SValentin Longchamp #endif
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