| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3288.c | 1081 ulong new_rate, gclk_rate; in rk3288_clk_get_rate() local
1086 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
1096 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1101 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1109 new_rate = rockchip_i2c_get_clk(priv->cru, clk->id); in rk3288_clk_get_rate()
1115 new_rate = rockchip_saradc_get_clk(priv->cru); in rk3288_clk_get_rate()
1118 new_rate = rockchip_tsadc_get_clk(priv->cru); in rk3288_clk_get_rate()
1121 new_rate = rockchip_aclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
1124 new_rate = rockchip_aclk_peri_get_clk(priv->cru); in rk3288_clk_get_rate()
1127 new_rate = rockchip_pclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
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| H A D | clk_rk3188.c | 505 ulong new_rate, gclk_rate; in rk3188_clk_get_rate() local
510 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3188_clk_get_rate()
518 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, in rk3188_clk_get_rate()
523 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, in rk3188_clk_get_rate()
533 new_rate = rk3188_saradc_get_clk(priv->cru); in rk3188_clk_get_rate()
538 return new_rate; in rk3188_clk_get_rate()
545 ulong new_rate; in rk3188_clk_set_rate() local
549 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
553 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
562 new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, in rk3188_clk_set_rate()
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| H A D | clk_rv1108.c | 599 ulong new_rate; in rv1108_clk_set_rate() local
603 new_rate = rv1108_mac_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
606 new_rate = rv1108_sfc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
609 new_rate = rv1108_saradc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
612 new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
615 new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
618 new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
621 new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
624 new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
627 new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
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| H A D | clk_rk3066.c | 475 ulong new_rate, gclk_rate; in rk3066_clk_get_rate() local
480 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3066_clk_get_rate()
485 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, in rk3066_clk_get_rate()
490 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, in rk3066_clk_get_rate()
503 return new_rate; in rk3066_clk_get_rate()
510 ulong new_rate; in rk3066_clk_set_rate() local
514 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3066_clk_set_rate()
518 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3066_clk_set_rate()
524 new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, in rk3066_clk_set_rate()
529 new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, in rk3066_clk_set_rate()
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| H A D | clk_rk3036.c | 516 ulong new_rate, gclk_rate; in rk3036_clk_set_rate() local
528 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
532 new_rate = rockchip_dclk_lcdc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
536 new_rate = rockchip_aclk_lcdc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
540 new_rate = rk3036_spi_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
544 new_rate = rk3036_peri_set_clk(priv, clk->id, gclk_rate, in rk3036_clk_set_rate()
551 return new_rate; in rk3036_clk_set_rate()
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| H A D | clk_rk3506.c | 207 static int rk3506_armclk_set_rate(struct rk3506_clk_priv *priv, ulong new_rate) in rk3506_armclk_set_rate() argument
214 rate = rockchip_get_cpu_settings(rk3506_cpu_rates, new_rate); in rk3506_armclk_set_rate()
224 if (new_rate >= old_rate) { in rk3506_armclk_set_rate()
231 if (new_rate == 589824000 || new_rate == 1179648000) { in rk3506_armclk_set_rate()
233 div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); in rk3506_armclk_set_rate()
235 } else if (new_rate == 903168000) { in rk3506_armclk_set_rate()
237 div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); in rk3506_armclk_set_rate()
241 div = DIV_ROUND_UP(priv->gpll_hz, new_rate); in rk3506_armclk_set_rate()
248 if (DIV_TO_RATE(prate, old_div) > new_rate) { in rk3506_armclk_set_rate()
260 if (new_rate < old_rate) { in rk3506_armclk_set_rate()
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| H A D | clk_rk3562.c | 155 static int rk3562_armclk_set_rate(struct rk3562_clk_priv *priv, ulong new_rate) in rk3562_armclk_set_rate() argument
161 rate = rockchip_get_cpu_settings(rk3562_cpu_rates, new_rate); in rk3562_armclk_set_rate()
172 if (old_rate == new_rate) { in rk3562_armclk_set_rate()
178 } else if (old_rate > new_rate) { in rk3562_armclk_set_rate()
180 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
187 } else if (old_rate < new_rate) { in rk3562_armclk_set_rate()
195 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
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| H A D | clk_rk3528.c | 195 static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate) in rk3528_armclk_set_clk() argument
201 rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate); in rk3528_armclk_set_clk()
211 if (old_rate > new_rate) { in rk3528_armclk_set_clk()
213 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
221 } else if (old_rate < new_rate) { in rk3528_armclk_set_clk()
229 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
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| H A D | clk_rk3368.c | 360 ulong new_rate = parent_rate / adj_div; in rk3368_mmc_find_best_rate_and_parent() local
370 if (new_rate <= best_rate) in rk3368_mmc_find_best_rate_and_parent()
374 best_rate = new_rate; in rk3368_mmc_find_best_rate_and_parent()
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| /rk3399_rockchip-uboot/drivers/clk/aspeed/ |
| H A D | clk_ast2500.c | 337 ulong new_rate; in ast2500_configure_d2pll() local
351 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); in ast2500_configure_d2pll()
374 return new_rate; in ast2500_configure_d2pll()
381 ulong new_rate; in ast2500_clk_set_rate() local
385 new_rate = ast2500_configure_ddr(priv->scu, rate); in ast2500_clk_set_rate()
388 new_rate = ast2500_configure_d2pll(priv->scu, rate); in ast2500_clk_set_rate()
394 return new_rate; in ast2500_clk_set_rate()
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_zynq.c | 293 ulong new_rate, best_rate = 0; in zynq_clk_calc_peripheral_two_divs() local
298 new_rate = DIV_ROUND_CLOSEST( in zynq_clk_calc_peripheral_two_divs()
300 new_err = abs(new_rate - rate); in zynq_clk_calc_peripheral_two_divs()
306 best_rate = new_rate; in zynq_clk_calc_peripheral_two_divs()
320 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
331 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
338 new_rate = DIV_ROUND_CLOSEST(rate, div0); in zynq_clk_set_peripheral_rate()
346 return new_rate; in zynq_clk_set_peripheral_rate()
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| H A D | clk_zynqmp.c | 428 ulong new_rate, best_rate = 0; in zynqmp_clk_calc_peripheral_two_divs() local
433 new_rate = DIV_ROUND_CLOSEST( in zynqmp_clk_calc_peripheral_two_divs()
435 new_err = abs(new_rate - rate); in zynqmp_clk_calc_peripheral_two_divs()
441 best_rate = new_rate; in zynqmp_clk_calc_peripheral_two_divs()
455 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
475 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
482 new_rate = DIV_ROUND_CLOSEST(rate, div0); in zynqmp_clk_set_peripheral_rate()
495 return new_rate; in zynqmp_clk_set_peripheral_rate()
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-core.c | 166 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
187 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
190 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
191 diff = abs(new_rate - rate); in peri_clk_set_rate()
194 c->rate = new_rate; in peri_clk_set_rate()
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-core.c | 166 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
187 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
190 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
191 diff = abs(new_rate - rate); in peri_clk_set_rate()
194 c->rate = new_rate; in peri_clk_set_rate()
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | phy-rockchip-samsung-hdptx-hdmi.c | 2037 ulong new_rate = -ENOENT; in hdptx_clk_set_rate() local
2047 new_rate = rate; in hdptx_clk_set_rate()
2052 new_rate = rate; in hdptx_clk_set_rate()
2058 new_rate = rate; in hdptx_clk_set_rate()
2063 return new_rate; in hdptx_clk_set_rate()
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