phy: rockchip-samsung-hdptx-hdmi: Remove phy/pll reset

These are ic debug reset, practically unusable.

Change-Id: I16c6f28d215b153e9974701ade33d137ae7351d6
Signed-off-by: Algea Cao <algea.cao@rock-

phy: rockchip-samsung-hdptx-hdmi: Remove phy/pll reset

These are ic debug reset, practically unusable.

Change-Id: I16c6f28d215b153e9974701ade33d137ae7351d6
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

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phy: rockchip-samsung-hdptx-hdmi: Registered phy pll clk does not rely on dts subnode

Registered phy pll clk does not rely on dts, otherwise
the presence of only devices in dts and no drivers in
ker

phy: rockchip-samsung-hdptx-hdmi: Registered phy pll clk does not rely on dts subnode

Registered phy pll clk does not rely on dts, otherwise
the presence of only devices in dts and no drivers in
kernel 6.1 is considered illegal.

Change-Id: I3a276d6d0849367a98029664be5565bf3a548c71
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

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phy: rockchip-samsung-hdptx-hdmi: Fix hdmi Inter-Pair Skew exceed the limits

In hdmi2.0 resolution, the phase of D2 lane is probabilistically
ahead of other lanes. Set phy deskew FIFO works on shar

phy: rockchip-samsung-hdptx-hdmi: Fix hdmi Inter-Pair Skew exceed the limits

In hdmi2.0 resolution, the phase of D2 lane is probabilistically
ahead of other lanes. Set phy deskew FIFO works on shared pointer
to fix this problem.

According to vendor, this patch is also available for frl mode.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I62337be15a68cb3289eddb4b8b6850eb810b0f25

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phy: phy-rockchip-samsung-hdptx: Reduce ROPLL loop bandwidth

24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through the low-pass loop
filter o

phy: phy-rockchip-samsung-hdptx: Reduce ROPLL loop bandwidth

24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through the low-pass loop
filter of ROPLL, resulting in hdmi flash. Reduce ROPLL loop bandwidth
can solve this problem.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I512f15272708fc8e2f812edc57dbc2765bb72d29

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drivers: video/phy: Add '\n' for message end

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I0ad57bb82a419f7583290fb167b1af34d0c91421

video/drm: phy-rockchip-samsung-hdptx-hdmi: Fix 4lanes * 8g frl mode cfg err

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I7dfa691744d89ff7d39e75989cc47af3f658cd2c

video/drm: phy-rockchip-samsung-hdptx-hdmi: solve the issue that memory is not freeed

Signed-off-by: Chen Shunqing <csq@rock-chips.com>
Change-Id: Idccf20cb8f45488c98315076f2c02364f489334a

phy: phy-rockchip-samsung-hdptx: FRL 8Gbps * 4 lanes mode use pll cascade mode

Vendor suggest FRL 8G * 4 lanes mode use ROPLL/LCPLL cascade mode.
ROPLL ref clock is from LCPLL.

Signed-off-by: Algea

phy: phy-rockchip-samsung-hdptx: FRL 8Gbps * 4 lanes mode use pll cascade mode

Vendor suggest FRL 8G * 4 lanes mode use ROPLL/LCPLL cascade mode.
ROPLL ref clock is from LCPLL.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I72ededdec20a87fc1a3245515bd09e902ee5cf58

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phy: phy-rockchip-samsung-hdptx: LCPLL is also used for low rate frl mode

In RK3588C, 24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through t

phy: phy-rockchip-samsung-hdptx: LCPLL is also used for low rate frl mode

In RK3588C, 24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through the low-pass loop
filter of ROPLL, resulting in hdmi clk jitter test fail.
The loop bandwidth of LCPLL is low, so LCPLL can be used to circumvent
this problem. RK3588 is also suitable for this scheme.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Iadd87adfddd284937ae9b6ffe2d83595ea7c6fcc

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phy: phy-rockchip-samsung-hdptx: Add function of enabling PLL independently in FRL mode

The phy pll must be enabled before access hdmi controller registers.
To support config hdmi controller registe

phy: phy-rockchip-samsung-hdptx: Add function of enabling PLL independently in FRL mode

The phy pll must be enabled before access hdmi controller registers.
To support config hdmi controller registers before phy output is
enabled, pll must be enabled separately in both TMDS and FRL mode.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9eb7df9e4d6d989e0ff752bd9e1d8433aba1ffa4

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phy: phy-rockchip-samsung-hdptx: Increase the poll times of phy lock

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I05a1c515b7e59d0560f463dac3f82ab607c7cdaf

video/drm: phy-rockchip-samsung-hdptx-hdmi: Improve signal quality

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I3e750620dfc7fcf6fa463bb7dfe6371647e885c6

video/drm: phy-rockchip-samsung-hdptx-hdmi: Fix 10 bit pll cfg err

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I07052507fb70c0482b95caab9a4c7789fa592162

video/drm: phy-rockchip-samsung-hdptx-hdmi: bind child node for clock

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I1a36542bc5c033c423d8ebceb234cc30741e8752

video/drm: phy-rockchip-samsung-hdptx-hdmi: Add PLL setting calculation

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I9f737fdd9f15e28e37d6f7f3976ed14396b00545

video/drm: phy-rockchip-samsung-hdptx-hdmi: Register phy pll as child device

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifd27057bca766aaab5b02280d6ffdc2828cef691

video/drm: Add samsung combphy hdmi driver

HDMI phy-pll may be used as dclk source.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id61ac5a9a04a8ec7068329c02567c33f3a2fe7c5