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Searched refs:ldr (Results 1 – 25 of 123) sorted by relevance

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/rk3399_rockchip-uboot/board/freescale/mx7ulp_evk/
H A Dplugin.S10 ldr r2, =0x403f0000
11 ldr r3, =0x00000000
14 ldr r2, =0x403e0000
15 ldr r3, =0x01000020
17 ldr r3, =0x01000000
19 ldr r3, =0x80808080
21 ldr r3, =0x00140000
23 ldr r3, =0x00000004
25 ldr r3, =0x00000002
27 ldr r3, =0x00000001
[all …]
/rk3399_rockchip-uboot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r0, =IOMUXC_BASE_ADDR
12 ldr r1, =0x000C0000
14 ldr r1, =0x00000000
16 ldr r1, =0x00000030
18 ldr r1, =0x00000030
22 ldr r1, =0x000C0030
25 ldr r1, =0x00000000
28 ldr r1, =0x00000030
33 ldr r1, =0x00020000
36 ldr r1, =0x00000030
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dlowlevel_init.S39 ldr r0, =EINT_ENABLE0
41 ldr r0, =EINT_ENABLE1
49 ldr r8, PSC_GEM_FLAG_CLEAR
50 ldr r6, MDCTL_GEM
51 ldr r7, [r6]
56 ldr r6, PTCMD
57 ldr r7, [r6]
63 ldr r6, PTSTAT
64 ldr r7, [r6]
70 ldr r6, MDSTAT_GEM
[all …]
/rk3399_rockchip-uboot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r0, =IOMUXC_BASE_ADDR
12 ldr r1, =0x00080000
14 ldr r1, =0x00000000
16 ldr r1, =0x00000030
20 ldr r1, =0x00020000
22 ldr r1, =0x00003030
28 ldr r1, =0x00020000
30 ldr r1, =0x00000030
40 ldr r1, =0x00082030
43 ldr r0, =MMDC_P0_BASE_ADDR
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S32 ldr x0, =GICD_BASE
34 ldr x1, =GICC_BASE
37 ldr x2, =DCFG_CCSR_SVR
38 ldr w2, [x2]
41 ldr w4, =SVR_DEV(SVR_LS1043A)
47 ldr x2, =SCFG_GIC400_ALIGN
48 ldr w2, [x2]
51 ldr x0, =GICD_BASE_64K
53 ldr x1, =GICC_BASE_64K
82 ldr x0, =CCI_AUX_CONTROL_BASE(20)
[all …]
/rk3399_rockchip-uboot/board/samsung/goni/
H A Dlowlevel_init.S31 ldr r7, =S5PC100_GPIO_BASE
32 ldr r8, =S5PC100_GPIO_BASE
34 ldr r2, =S5PC110_PRO_ID
35 ldr r0, [r2]
40 ldr r8, =S5PC110_GPIO_BASE
46 ldr r0, =S5PC110_RST_STAT
47 ldr r1, [r0]
56 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
61 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
87 ldr r0, =0xe0f00000
[all …]
/rk3399_rockchip-uboot/board/armadeus/apf27/
H A Dlowlevel_init.S23 ldr r0, =GPCR
24 ldr r1, =ACFG_GPCR_VAL
25 ldr r5, [r0]
32 ldr r0, =CSCR
34 ldr r1, [r0]
65 ldr r0, =IMX_ESD_BASE
66 ldr r4, =ESDMISC_SDRAM_RDY
67 2: ldr r1, [r0, #ESDMISC_ROF]
72 ldr r0, =IMX_ESD_BASE
73 ldr r4, =ACFG_ESDMISC_VAL
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S30 ldr r3, =SDRAM_BASE
47 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
59 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
66 ldr r4, =0x10
78 ldr r4, =0x01e0
82 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
87 ldr r4, [r2]
90 ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
105 ldr r1, =0xf00dface
106 ldr r2, =0xdeadbeef
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dlowlevel_init.S33 ldr r0, =0xC0 | /* tag RAM */ \
40 ldr r3, [r4, #ROM_SI_REV]
63 ldr r0, =AIPS1_BASE_ADDR
64 ldr r1, =0x77777777
67 ldr r0, =AIPS2_BASE_ADDR
83 ldr r0, =M4IF_BASE_ADDR
85 ldr r1, =0x00000203
90 ldr r1, =0x00120125
93 ldr r1, =0x001901A3
100 ldr r0, =\pll
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dspr_lowlevel_init.S26 ldr sp,SRAM_STACK_V
33 ldr r0,DDR_07_V
34 ldr r1,[r0]
35 ldr r2,DDR_ACTIVE_V
38 ldr r0,DDR_57_V
39 ldr r1,[r0]
40 ldr r2,CYCLES_MASK_V
42 ldr r2,REFRESH_CYCLES_V
45 ldr r0,DDR_07_V
46 ldr r1,[r0]
[all …]
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Dlowlevel_init.S10 ldr r2, =\reg
11 ldr r3, =\val
16 ldr r2, =\reg
17 ldr r3, =\val
22 ldr r2, =\loops
36 ldr r0, =0x43F00000
37 ldr r1, =0x77777777
40 ldr r0, =0x53F00000
49 ldr r0, =0x43F00000
50 ldr r1, =0x0
[all …]
/rk3399_rockchip-uboot/board/samsung/smdkc100/
H A Dlowlevel_init.S26 ldr r8, =S5PC100_GPIO_BASE
29 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
34 ldr r0, =S5PC100_SROMC_BASE
35 ldr r1, =0x9
39 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
41 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
74 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
77 ldr r1, =0x00011110
79 ldr r1, =0x1
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Ddebug_ll.S24 ldr r0, =SG_REVISION
25 ldr r1, [r0]
34 ldr r0, =SG_IECTRL
35 ldr r1, [r0]
41 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
53 ldr r0, =SG_LOADPINCTRL
57 ldr r0, =SC_CLKCTRL
58 ldr r1, [r0]
62 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
72 ldr r0, =SG_IECTRL
[all …]
/rk3399_rockchip-uboot/drivers/rkflash/
H A Drk_sftl_arm_v7.S31 ldr r3, .L3
113 ldr r3, .L10
117 ldr r2, .L10+4
119 ldr r3, .L10+8
123 ldr r2, .L10+12
126 ldr r2, .L10+16
129 ldr r2, .L10+20
130 ldr r2, [r2]
132 ldr r2, .L10+24
161 ldr r2, .L23
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S76 ldr r4, =ORION5X_REGS_PHY_BASE
80 ldr r3, =0xD0000000
88 ldr r6, =0x00000001
95 ldr r6, =0x00000030
109 ldr r6, =SDRAM_CONFIG
113 ldr r6, =SDRAM_CONTROL
117 ldr r6, =SDRAM_ADDR_CTRL
121 ldr r6, =SDRAM_BANK0_SIZE
126 ldr r6, =SDRAM_OPEN_PAGE_EN
130 ldr r6, =SDRAM_TIME_CTRL_LOW
[all …]
/rk3399_rockchip-uboot/drivers/rknand/
H A Drk_zftl_arm_v7.S61 ldr r3, .L16
62 ldr r7, .L16+4
68 ldr r3, .L16+8
84 ldr r3, .L16+12
108 ldr r6, .L26
113 ldr r7, [r6]
118 ldr r3, [r0]
131 ldr r1, .L26+4
132 ldr r0, .L26+8
135 ldr r3, [r10]
[all …]
H A Drk_ftl_arm_v7.S31 ldr r3, .L2
33 ldr r4, [r3, r0, lsl #3]
41 ldr r3, [r4, #2048]
42 ldr r0, [r4, #2048]
48 ldr r3, [r4, #2048]
53 ldr r0, [r4, #2048]
75 ldr r3, .L5
78 ldr r2, [r3]
81 ldr r3, [r2, r1, lsl #2]
101 ldr r3, .L15
[all …]
/rk3399_rockchip-uboot/board/syteco/zmx25/
H A Dlowlevel_init.S44 ldr r0, =IMX_ESDRAMC_BASE
45 ldr r2, =IMX_SDRAM_BANK0_BASE
51 ldr r1, =(1 << 1) | (1 << 2)
53 1: ldr r3, [r0, #ESDRAMC_ESDMISC]
56 ldr r1, =(1 << 2)
59 ldr r1, =0x002a7420
63 ldr r1, =0x92216008
69 ldr r1, =0xa2216008
72 ldr r3, [r2]
73 ldr r3, [r2]
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm926ejs/
H A Dlowlevel_init.S35 ldr r0, =POS1 /* r0 = POS1 compile */
39 ldr r0, =SMRDATA
40 ldr r2, =SMRDATA1
45 ldr r1, [r0], #4
47 ldr r3, [r0], #4
58 ldr r1, =(AT91_ASM_PMC_MCKR)
59 ldr r0, [r1]
68 ldr r1, =(AT91_ASM_PMC_MOR)
69 ldr r2, =(AT91_ASM_PMC_SR)
71 ldr r0, =CONFIG_SYS_MOR_VAL
[all …]
/rk3399_rockchip-uboot/board/freescale/mx35pdk/
H A Dlowlevel_init.S22 ldr \tmp, =IIM_BASE_ADDR
23 ldr \ret, [\tmp, #IIM_SREV]
33 ldr r0, =DBG_BASE_ADDR
34 ldr r1, =DBG_CSCR_U_CONFIG
36 ldr r1, =DBG_CSCR_L_CONFIG
38 ldr r1, =DBG_CSCR_A_CONFIG
44 ldr r0, =CCM_BASE_ADDR
47 ldr r1, [r0, #CLKCTL_COSR]
55 ldr r2, =CCM_CCMR_CONFIG
62 ldr r2, [r0, #CLKCTL_PDR0]
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/
H A Dmx6_plugin.S47 ldr r3, =ROM_VERSION_OFFSET
48 ldr r4, [r3]
51 ldr r3, =0x00900b00
52 ldr r4, =0x50000000
55 ldr r3, =0x00900800
56 ldr r4, =0x08000000
65 ldr r3, =ROM_VERSION_OFFSET
66 ldr r4, [r3]
68 ldr r3, =ROM_VERSION_TO12
73 ldr r3, =ROM_VERSION_TO15
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dmx7_plugin.S25 ldr r0, =0x30384680
26 ldr r1, [r0]
30 ldr r0, =0x30B10158
31 ldr r1, [r0]
58 ldr r3, =ROM_VERSION_OFFSET
59 ldr r4, [r3]
60 ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
61 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
73 ldr r5, boot_data2
75 ldr r5, image_len2
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dcrt0.S74 ldr r0, =(CONFIG_TPL_STACK)
76 ldr r0, =(CONFIG_SPL_STACK)
78 ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
99 ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */
102 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */
107 ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */
112 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
145 ldr r0, =__bss_start /* this is auto-relocated! */
148 ldr r3, =__bss_end /* this is auto-relocated! */
154 ldr r1, =__bss_end /* this is auto-relocated! */
[all …]
H A Dcrt0_64.S74 ldr x0, =(CONFIG_TPL_STACK)
76 ldr x0, =(CONFIG_SPL_STACK)
78 ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
98 ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
100 ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
107 ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
112 ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
114 ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */
144 ldr x0, =__bss_start /* this is auto-relocated! */
145 ldr x1, =__bss_end /* this is auto-relocated! */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dlowlevel_init.S23 ldr r0, =0x0000003D
24 ldr r1, =0x40004040
28 ldr r0, =0x0001401E
29 ldr r1, =0x40004058
34 ldr r0, [r1]
39 ldr r1, =0x40004044
40 ldr r0, [r1]

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