18bc4ee9eSMinkyu Kang/* 28bc4ee9eSMinkyu Kang * Copyright (C) 2009 Samsung Electronics 38bc4ee9eSMinkyu Kang * Kyungmin Park <kyungmin.park@samsung.com> 48bc4ee9eSMinkyu Kang * Minkyu Kang <mk7.kang@samsung.com> 58bc4ee9eSMinkyu Kang * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 78bc4ee9eSMinkyu Kang */ 88bc4ee9eSMinkyu Kang 98bc4ee9eSMinkyu Kang#include <config.h> 108bc4ee9eSMinkyu Kang#include <asm/arch/cpu.h> 118bc4ee9eSMinkyu Kang#include <asm/arch/power.h> 128bc4ee9eSMinkyu Kang 138bc4ee9eSMinkyu Kang/* 148bc4ee9eSMinkyu Kang * Register usages: 158bc4ee9eSMinkyu Kang * 168bc4ee9eSMinkyu Kang * r5 has zero always 178bc4ee9eSMinkyu Kang */ 188bc4ee9eSMinkyu Kang 198bc4ee9eSMinkyu Kang .globl lowlevel_init 208bc4ee9eSMinkyu Kanglowlevel_init: 218bc4ee9eSMinkyu Kang mov r9, lr 228bc4ee9eSMinkyu Kang 238bc4ee9eSMinkyu Kang /* r5 has always zero */ 248bc4ee9eSMinkyu Kang mov r5, #0 258bc4ee9eSMinkyu Kang 268bc4ee9eSMinkyu Kang ldr r8, =S5PC100_GPIO_BASE 278bc4ee9eSMinkyu Kang 288bc4ee9eSMinkyu Kang /* Disable Watchdog */ 298bc4ee9eSMinkyu Kang ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000 308bc4ee9eSMinkyu Kang orr r0, r0, #0x0 318bc4ee9eSMinkyu Kang str r5, [r0] 328bc4ee9eSMinkyu Kang 338bc4ee9eSMinkyu Kang /* setting SRAM */ 348bc4ee9eSMinkyu Kang ldr r0, =S5PC100_SROMC_BASE 358bc4ee9eSMinkyu Kang ldr r1, =0x9 368bc4ee9eSMinkyu Kang str r1, [r0] 378bc4ee9eSMinkyu Kang 388bc4ee9eSMinkyu Kang /* S5PC100 has 3 groups of interrupt sources */ 398bc4ee9eSMinkyu Kang ldr r0, =S5PC100_VIC0_BASE @0xE4000000 408bc4ee9eSMinkyu Kang ldr r1, =S5PC100_VIC1_BASE @0xE4000000 418bc4ee9eSMinkyu Kang ldr r2, =S5PC100_VIC2_BASE @0xE4000000 428bc4ee9eSMinkyu Kang 438bc4ee9eSMinkyu Kang /* Disable all interrupts (VIC0, VIC1 and VIC2) */ 448bc4ee9eSMinkyu Kang mvn r3, #0x0 458bc4ee9eSMinkyu Kang str r3, [r0, #0x14] @INTENCLEAR 468bc4ee9eSMinkyu Kang str r3, [r1, #0x14] @INTENCLEAR 478bc4ee9eSMinkyu Kang str r3, [r2, #0x14] @INTENCLEAR 488bc4ee9eSMinkyu Kang 498bc4ee9eSMinkyu Kang /* Set all interrupts as IRQ */ 508bc4ee9eSMinkyu Kang str r5, [r0, #0xc] @INTSELECT 518bc4ee9eSMinkyu Kang str r5, [r1, #0xc] @INTSELECT 528bc4ee9eSMinkyu Kang str r5, [r2, #0xc] @INTSELECT 538bc4ee9eSMinkyu Kang 548bc4ee9eSMinkyu Kang /* Pending Interrupt Clear */ 558bc4ee9eSMinkyu Kang str r5, [r0, #0xf00] @INTADDRESS 568bc4ee9eSMinkyu Kang str r5, [r1, #0xf00] @INTADDRESS 578bc4ee9eSMinkyu Kang str r5, [r2, #0xf00] @INTADDRESS 588bc4ee9eSMinkyu Kang 598bc4ee9eSMinkyu Kang /* for UART */ 608bc4ee9eSMinkyu Kang bl uart_asm_init 618bc4ee9eSMinkyu Kang 628bc4ee9eSMinkyu Kang /* for TZPC */ 638bc4ee9eSMinkyu Kang bl tzpc_asm_init 648bc4ee9eSMinkyu Kang 658bc4ee9eSMinkyu Kang1: 668bc4ee9eSMinkyu Kang mov lr, r9 678bc4ee9eSMinkyu Kang mov pc, lr 688bc4ee9eSMinkyu Kang 698bc4ee9eSMinkyu Kang/* 708bc4ee9eSMinkyu Kang * system_clock_init: Initialize core clock and bus clock. 718bc4ee9eSMinkyu Kang * void system_clock_init(void) 728bc4ee9eSMinkyu Kang */ 738bc4ee9eSMinkyu Kangsystem_clock_init: 74d93d0f0cSMinkyu Kang ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 758bc4ee9eSMinkyu Kang 768bc4ee9eSMinkyu Kang /* Set Clock divider */ 778bc4ee9eSMinkyu Kang ldr r1, =0x00011110 788bc4ee9eSMinkyu Kang str r1, [r8, #0x304] 798bc4ee9eSMinkyu Kang ldr r1, =0x1 808bc4ee9eSMinkyu Kang str r1, [r8, #0x308] 818bc4ee9eSMinkyu Kang ldr r1, =0x00011301 828bc4ee9eSMinkyu Kang str r1, [r8, #0x300] 838bc4ee9eSMinkyu Kang 848bc4ee9eSMinkyu Kang /* Set Lock Time */ 858bc4ee9eSMinkyu Kang ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 868bc4ee9eSMinkyu Kang str r1, [r8, #0x000] @ APLL_LOCK 878bc4ee9eSMinkyu Kang str r1, [r8, #0x004] @ MPLL_LOCK 888bc4ee9eSMinkyu Kang str r1, [r8, #0x008] @ EPLL_LOCK 898bc4ee9eSMinkyu Kang str r1, [r8, #0x00C] @ HPLL_LOCK 908bc4ee9eSMinkyu Kang 918bc4ee9eSMinkyu Kang /* APLL_CON */ 928bc4ee9eSMinkyu Kang ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz) 938bc4ee9eSMinkyu Kang str r1, [r8, #0x100] 948bc4ee9eSMinkyu Kang /* MPLL_CON */ 958bc4ee9eSMinkyu Kang ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) 968bc4ee9eSMinkyu Kang str r1, [r8, #0x104] 978bc4ee9eSMinkyu Kang /* EPLL_CON */ 988bc4ee9eSMinkyu Kang ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) 998bc4ee9eSMinkyu Kang str r1, [r8, #0x108] 1008bc4ee9eSMinkyu Kang /* HPLL_CON */ 1018bc4ee9eSMinkyu Kang ldr r1, =0x80600603 1028bc4ee9eSMinkyu Kang str r1, [r8, #0x10C] 1038bc4ee9eSMinkyu Kang 1048bc4ee9eSMinkyu Kang /* Set Source Clock */ 1058bc4ee9eSMinkyu Kang ldr r1, =0x1111 @ A, M, E, HPLL Muxing 1068bc4ee9eSMinkyu Kang str r1, [r8, #0x200] @ CLK_SRC0 1078bc4ee9eSMinkyu Kang 1088bc4ee9eSMinkyu Kang ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing 1098bc4ee9eSMinkyu Kang str r1, [r8, #0x204] @ CLK_SRC1 1108bc4ee9eSMinkyu Kang 1118bc4ee9eSMinkyu Kang ldr r1, =0x9000 @ ARMCLK/4 1128bc4ee9eSMinkyu Kang str r1, [r8, #0x400] @ CLK_OUT 1138bc4ee9eSMinkyu Kang 1148bc4ee9eSMinkyu Kang /* wait at least 200us to stablize all clock */ 1158bc4ee9eSMinkyu Kang mov r2, #0x10000 1168bc4ee9eSMinkyu Kang1: subs r2, r2, #1 1178bc4ee9eSMinkyu Kang bne 1b 1188bc4ee9eSMinkyu Kang 1198bc4ee9eSMinkyu Kang mov pc, lr 1208bc4ee9eSMinkyu Kang 1218bc4ee9eSMinkyu Kang/* 1228bc4ee9eSMinkyu Kang * uart_asm_init: Initialize UART's pins 1238bc4ee9eSMinkyu Kang */ 1248bc4ee9eSMinkyu Kanguart_asm_init: 1258bc4ee9eSMinkyu Kang mov r0, r8 1268bc4ee9eSMinkyu Kang ldr r1, =0x22222222 1278bc4ee9eSMinkyu Kang str r1, [r0, #0x0] @ GPA0_CON 1288bc4ee9eSMinkyu Kang ldr r1, =0x00022222 1298bc4ee9eSMinkyu Kang str r1, [r0, #0x20] @ GPA1_CON 1308bc4ee9eSMinkyu Kang 1318bc4ee9eSMinkyu Kang mov pc, lr 1328bc4ee9eSMinkyu Kang 1338bc4ee9eSMinkyu Kang/* 1348bc4ee9eSMinkyu Kang * tzpc_asm_init: Initialize TZPC 1358bc4ee9eSMinkyu Kang */ 1368bc4ee9eSMinkyu Kangtzpc_asm_init: 1378bc4ee9eSMinkyu Kang ldr r0, =0xE3800000 1388bc4ee9eSMinkyu Kang mov r1, #0x0 1398bc4ee9eSMinkyu Kang str r1, [r0] 1408bc4ee9eSMinkyu Kang mov r1, #0xff 1418bc4ee9eSMinkyu Kang str r1, [r0, #0x804] 1428bc4ee9eSMinkyu Kang str r1, [r0, #0x810] 1438bc4ee9eSMinkyu Kang 1448bc4ee9eSMinkyu Kang ldr r0, =0xE2800000 1458bc4ee9eSMinkyu Kang str r1, [r0, #0x804] 1468bc4ee9eSMinkyu Kang str r1, [r0, #0x810] 1478bc4ee9eSMinkyu Kang str r1, [r0, #0x81C] 1488bc4ee9eSMinkyu Kang 1498bc4ee9eSMinkyu Kang ldr r0, =0xE2900000 1508bc4ee9eSMinkyu Kang str r1, [r0, #0x804] 1518bc4ee9eSMinkyu Kang str r1, [r0, #0x810] 1528bc4ee9eSMinkyu Kang 1538bc4ee9eSMinkyu Kang mov pc, lr 154