1412ae53aSAlbert ARIBAUD \(3ADEV\)/* 2412ae53aSAlbert ARIBAUD \(3ADEV\) * WORK Microwave work_92105 board low level init 3412ae53aSAlbert ARIBAUD \(3ADEV\) * 4412ae53aSAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2014 DENX Software Engineering GmbH 5412ae53aSAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6412ae53aSAlbert ARIBAUD \(3ADEV\) * 7412ae53aSAlbert ARIBAUD \(3ADEV\) * Low level init is called from SPL to set up the clocks. 8412ae53aSAlbert ARIBAUD \(3ADEV\) * On entry, the LPC3250 is in Direct Run mode with all clocks 9412ae53aSAlbert ARIBAUD \(3ADEV\) * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is 10412ae53aSAlbert ARIBAUD \(3ADEV\) * 104 MHz and PCLK is 13 MHz. 11412ae53aSAlbert ARIBAUD \(3ADEV\) * 12412ae53aSAlbert ARIBAUD \(3ADEV\) * This code must run from SRAM so that the clock changes do 13412ae53aSAlbert ARIBAUD \(3ADEV\) * not prevent it from executing. 14412ae53aSAlbert ARIBAUD \(3ADEV\) * 15412ae53aSAlbert ARIBAUD \(3ADEV\) * SPDX-License-Identifier: GPL-2.0+ 16412ae53aSAlbert ARIBAUD \(3ADEV\) */ 17412ae53aSAlbert ARIBAUD \(3ADEV\) 18412ae53aSAlbert ARIBAUD \(3ADEV\).globl lowlevel_init 19412ae53aSAlbert ARIBAUD \(3ADEV\) 20412ae53aSAlbert ARIBAUD \(3ADEV\)lowlevel_init: 21412ae53aSAlbert ARIBAUD \(3ADEV\) 22412ae53aSAlbert ARIBAUD \(3ADEV\) /* Set ARM, HCLK, PCLK dividers for normal mode */ 23412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r0, =0x0000003D 24412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r1, =0x40004040 25412ae53aSAlbert ARIBAUD \(3ADEV\) str r0, [r1] 26412ae53aSAlbert ARIBAUD \(3ADEV\) 27412ae53aSAlbert ARIBAUD \(3ADEV\) /* Start HCLK PLL for 208 MHz */ 28412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r0, =0x0001401E 29412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r1, =0x40004058 30412ae53aSAlbert ARIBAUD \(3ADEV\) str r0, [r1] 31412ae53aSAlbert ARIBAUD \(3ADEV\) 32412ae53aSAlbert ARIBAUD \(3ADEV\) /* wait for HCLK PLL to lock */ 33412ae53aSAlbert ARIBAUD \(3ADEV\)1: 34412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r0, [r1] 35412ae53aSAlbert ARIBAUD \(3ADEV\) ands r0, r0, #1 36412ae53aSAlbert ARIBAUD \(3ADEV\) beq 1b 37412ae53aSAlbert ARIBAUD \(3ADEV\) 38412ae53aSAlbert ARIBAUD \(3ADEV\) /* switch to normal mode */ 39412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r1, =0x40004044 40412ae53aSAlbert ARIBAUD \(3ADEV\) ldr r0, [r1] 41412ae53aSAlbert ARIBAUD \(3ADEV\) orr r0, #0x00000004 42412ae53aSAlbert ARIBAUD \(3ADEV\) str r0, [r1] 43412ae53aSAlbert ARIBAUD \(3ADEV\) 44*a187559eSBin Meng /* Return to U-Boot via saved link register */ 45412ae53aSAlbert ARIBAUD \(3ADEV\) mov pc, lr 46