Lines Matching refs:ldr
26 ldr sp,SRAM_STACK_V
33 ldr r0,DDR_07_V
34 ldr r1,[r0]
35 ldr r2,DDR_ACTIVE_V
38 ldr r0,DDR_57_V
39 ldr r1,[r0]
40 ldr r2,CYCLES_MASK_V
42 ldr r2,REFRESH_CYCLES_V
45 ldr r0,DDR_07_V
46 ldr r1,[r0]
47 ldr r2,SREFRESH_MASK_V
56 ldr r0,SREFRESH_DELAY_V
63 ldr r0,SCCTRL_V
75 ldr r6,PLL2_FREQ_V
76 ldr r7,PLL2_CNTL_V
81 ldr r6,PLL1_FREQ_V
82 ldr r7,PLL1_CNTL_V
86 ldr r1,[r0]
87 ldr r2,PLLFREQ_MASK_V
94 ldr r1,P1C0A_V
96 ldr r1,P1C0E_V
98 ldr r1,P1C06_V
100 ldr r1,P1C0E_V
104 ldr r1,[r0]
110 ldr r0,SCCTRL_V
115 ldr r0,DDR_07_V
116 ldr r1,[R0]
117 ldr r2,SREFRESH_MASK_V
120 ldr r2,DDR_ACTIVE_V
125 ldr r0,SREFRESH_DELAY_V