139f0023eSMatthias Weisser/* 239f0023eSMatthias Weisser * (C) Copyright 2011 339f0023eSMatthias Weisser * Matthias Weisser <weisserm@arcor.de> 439f0023eSMatthias Weisser * 539f0023eSMatthias Weisser * (C) Copyright 2009 DENX Software Engineering 639f0023eSMatthias Weisser * Author: John Rigby <jrigby@gmail.com> 739f0023eSMatthias Weisser * 839f0023eSMatthias Weisser * Based on U-Boot and RedBoot sources for several different i.mx 939f0023eSMatthias Weisser * platforms. 1039f0023eSMatthias Weisser * 11*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1239f0023eSMatthias Weisser */ 1339f0023eSMatthias Weisser 1439f0023eSMatthias Weisser#include <asm/macro.h> 1539f0023eSMatthias Weisser#include <asm/arch/macro.h> 1639f0023eSMatthias Weisser#include <asm/arch/imx-regs.h> 17a4814a69SStefano Babic#include <generated/asm-offsets.h> 1839f0023eSMatthias Weisser 1939f0023eSMatthias Weisser/* 2039f0023eSMatthias Weisser * clocks 2139f0023eSMatthias Weisser */ 2239f0023eSMatthias Weisser.macro init_clocks 2339f0023eSMatthias Weisser 2439f0023eSMatthias Weisser /* disable clock output */ 2539f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 2639f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 2739f0023eSMatthias Weisser 2839f0023eSMatthias Weisser /* 2939f0023eSMatthias Weisser * enable all implemented clocks in all three 3039f0023eSMatthias Weisser * clock control registers 3139f0023eSMatthias Weisser */ 3239f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff 3339f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff 3439f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff 3539f0023eSMatthias Weisser 3639f0023eSMatthias Weisser /* Devide NAND clock by 32 */ 3739f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F 3839f0023eSMatthias Weisser.endm 3939f0023eSMatthias Weisser 4039f0023eSMatthias Weisser/* 4139f0023eSMatthias Weisser * sdram controller init 4239f0023eSMatthias Weisser */ 4339f0023eSMatthias Weisser.macro init_lpddr 4439f0023eSMatthias Weisser ldr r0, =IMX_ESDRAMC_BASE 4539f0023eSMatthias Weisser ldr r2, =IMX_SDRAM_BANK0_BASE 4639f0023eSMatthias Weisser 4739f0023eSMatthias Weisser /* 4839f0023eSMatthias Weisser * reset SDRAM controller 4939f0023eSMatthias Weisser * then wait for initialization to complete 5039f0023eSMatthias Weisser */ 5139f0023eSMatthias Weisser ldr r1, =(1 << 1) | (1 << 2) 5239f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDMISC] 5339f0023eSMatthias Weisser1: ldr r3, [r0, #ESDRAMC_ESDMISC] 5439f0023eSMatthias Weisser tst r3, #(1 << 31) 5539f0023eSMatthias Weisser beq 1b 5639f0023eSMatthias Weisser ldr r1, =(1 << 2) 5739f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDMISC] 5839f0023eSMatthias Weisser 5939f0023eSMatthias Weisser ldr r1, =0x002a7420 6039f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCFG0] 6139f0023eSMatthias Weisser 6239f0023eSMatthias Weisser /* control | precharge */ 6339f0023eSMatthias Weisser ldr r1, =0x92216008 6439f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 6539f0023eSMatthias Weisser /* dram command encoded in address */ 6639f0023eSMatthias Weisser str r1, [r2, #0x400] 6739f0023eSMatthias Weisser 6839f0023eSMatthias Weisser /* auto refresh */ 6939f0023eSMatthias Weisser ldr r1, =0xa2216008 7039f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 7139f0023eSMatthias Weisser /* read dram twice to auto refresh */ 7239f0023eSMatthias Weisser ldr r3, [r2] 7339f0023eSMatthias Weisser ldr r3, [r2] 7439f0023eSMatthias Weisser 7539f0023eSMatthias Weisser /* control | load mode */ 7639f0023eSMatthias Weisser ldr r1, =0xb2216008 7739f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 7839f0023eSMatthias Weisser 7939f0023eSMatthias Weisser /* mode register of lpddram */ 8039f0023eSMatthias Weisser strb r1, [r2, #0x33] 8139f0023eSMatthias Weisser 8239f0023eSMatthias Weisser /* extended mode register of lpddrram */ 8339f0023eSMatthias Weisser ldr r2, =0x81000000 8439f0023eSMatthias Weisser strb r1, [r2] 8539f0023eSMatthias Weisser 8639f0023eSMatthias Weisser /* control | normal */ 8739f0023eSMatthias Weisser ldr r1, =0x82216008 8839f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 8939f0023eSMatthias Weisser.endm 9039f0023eSMatthias Weisser 9139f0023eSMatthias Weisser.globl lowlevel_init 9239f0023eSMatthias Weisserlowlevel_init: 9339f0023eSMatthias Weisser init_aips 9439f0023eSMatthias Weisser init_max 9539f0023eSMatthias Weisser init_clocks 9639f0023eSMatthias Weisser init_lpddr 9739f0023eSMatthias Weisser mov pc, lr 98