1fe5ea57bSMasahiro Yamada/* 2fe5ea57bSMasahiro Yamada * On-chip UART initializaion for low-level debugging 3fe5ea57bSMasahiro Yamada * 4fe5ea57bSMasahiro Yamada * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 5fe5ea57bSMasahiro Yamada * 6fe5ea57bSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 7fe5ea57bSMasahiro Yamada */ 8fe5ea57bSMasahiro Yamada 9fe5ea57bSMasahiro Yamada#include <linux/serial_reg.h> 10fe5ea57bSMasahiro Yamada#include <linux/linkage.h> 11fe5ea57bSMasahiro Yamada 12fe5ea57bSMasahiro Yamada#include "../bcu/bcu-regs.h" 13fe5ea57bSMasahiro Yamada#include "../sc-regs.h" 14fe5ea57bSMasahiro Yamada#include "../sg-regs.h" 15fe5ea57bSMasahiro Yamada 16fe5ea57bSMasahiro Yamada#if !defined(CONFIG_DEBUG_SEMIHOSTING) 17fe5ea57bSMasahiro Yamada#include CONFIG_DEBUG_LL_INCLUDE 18fe5ea57bSMasahiro Yamada#endif 19fe5ea57bSMasahiro Yamada 20fe5ea57bSMasahiro Yamada#define BAUDRATE 115200 21fe5ea57bSMasahiro Yamada#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) 22fe5ea57bSMasahiro Yamada 23fe5ea57bSMasahiro YamadaENTRY(debug_ll_init) 24fe5ea57bSMasahiro Yamada ldr r0, =SG_REVISION 25fe5ea57bSMasahiro Yamada ldr r1, [r0] 26fe5ea57bSMasahiro Yamada and r1, r1, #SG_REVISION_TYPE_MASK 27fe5ea57bSMasahiro Yamada mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT 28fe5ea57bSMasahiro Yamada 29ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_LD4) 30ea65c980SMasahiro Yamada#define UNIPHIER_LD4_UART_CLK 36864000 31fe5ea57bSMasahiro Yamada cmp r1, #0x26 32*5b660066SMasahiro Yamada bne ld4_end 33fe5ea57bSMasahiro Yamada 34fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 35fe5ea57bSMasahiro Yamada ldr r1, [r0] 36fe5ea57bSMasahiro Yamada orr r1, r1, #1 37fe5ea57bSMasahiro Yamada str r1, [r0] 38fe5ea57bSMasahiro Yamada 39fe5ea57bSMasahiro Yamada sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0 40fe5ea57bSMasahiro Yamada 41ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE) 42fe5ea57bSMasahiro Yamada 43fe5ea57bSMasahiro Yamada b init_uart 44*5b660066SMasahiro Yamadald4_end: 45fe5ea57bSMasahiro Yamada#endif 46ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PRO4) 47ea65c980SMasahiro Yamada#define UNIPHIER_PRO4_UART_CLK 73728000 48fe5ea57bSMasahiro Yamada cmp r1, #0x28 49*5b660066SMasahiro Yamada bne pro4_end 50fe5ea57bSMasahiro Yamada 51fe5ea57bSMasahiro Yamada sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 52fe5ea57bSMasahiro Yamada 53fe5ea57bSMasahiro Yamada ldr r0, =SG_LOADPINCTRL 54fe5ea57bSMasahiro Yamada mov r1, #1 55fe5ea57bSMasahiro Yamada str r1, [r0] 56fe5ea57bSMasahiro Yamada 57fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 58fe5ea57bSMasahiro Yamada ldr r1, [r0] 59fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 60fe5ea57bSMasahiro Yamada str r1, [r0] 61fe5ea57bSMasahiro Yamada 62ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE) 63fe5ea57bSMasahiro Yamada 64fe5ea57bSMasahiro Yamada b init_uart 65*5b660066SMasahiro Yamadapro4_end: 66fe5ea57bSMasahiro Yamada#endif 67ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_SLD8) 68ea65c980SMasahiro Yamada#define UNIPHIER_SLD8_UART_CLK 80000000 69fe5ea57bSMasahiro Yamada cmp r1, #0x29 70*5b660066SMasahiro Yamada bne sld8_end 71fe5ea57bSMasahiro Yamada 72fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 73fe5ea57bSMasahiro Yamada ldr r1, [r0] 74fe5ea57bSMasahiro Yamada orr r1, r1, #1 75fe5ea57bSMasahiro Yamada str r1, [r0] 76fe5ea57bSMasahiro Yamada 77fe5ea57bSMasahiro Yamada sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0 78fe5ea57bSMasahiro Yamada 79ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE) 80fe5ea57bSMasahiro Yamada 81fe5ea57bSMasahiro Yamada b init_uart 82*5b660066SMasahiro Yamadasld8_end: 83fe5ea57bSMasahiro Yamada#endif 84ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PRO5) 85ea65c980SMasahiro Yamada#define UNIPHIER_PRO5_UART_CLK 73728000 86fe5ea57bSMasahiro Yamada cmp r1, #0x2A 87*5b660066SMasahiro Yamada bne pro5_end 88fe5ea57bSMasahiro Yamada 89fe5ea57bSMasahiro Yamada sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 90fe5ea57bSMasahiro Yamada sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1 91fe5ea57bSMasahiro Yamada sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 92fe5ea57bSMasahiro Yamada sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 93fe5ea57bSMasahiro Yamada 94fe5ea57bSMasahiro Yamada ldr r0, =SG_LOADPINCTRL 95fe5ea57bSMasahiro Yamada mov r1, #1 96fe5ea57bSMasahiro Yamada str r1, [r0] 97fe5ea57bSMasahiro Yamada 98fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 99fe5ea57bSMasahiro Yamada ldr r1, [r0] 100fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 101fe5ea57bSMasahiro Yamada str r1, [r0] 102fe5ea57bSMasahiro Yamada 103ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE) 104fe5ea57bSMasahiro Yamada 105fe5ea57bSMasahiro Yamada b init_uart 106*5b660066SMasahiro Yamadapro5_end: 107fe5ea57bSMasahiro Yamada#endif 108ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PXS2) 109ea65c980SMasahiro Yamada#define UNIPHIER_PXS2_UART_CLK 88900000 110fe5ea57bSMasahiro Yamada cmp r1, #0x2E 111*5b660066SMasahiro Yamada bne pxs2_end 112fe5ea57bSMasahiro Yamada 113fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 114fe5ea57bSMasahiro Yamada ldr r1, [r0] 115fe5ea57bSMasahiro Yamada orr r1, r1, #1 116fe5ea57bSMasahiro Yamada str r1, [r0] 117fe5ea57bSMasahiro Yamada 118fe5ea57bSMasahiro Yamada sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0 119fe5ea57bSMasahiro Yamada sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1 120fe5ea57bSMasahiro Yamada sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 121fe5ea57bSMasahiro Yamada sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 122fe5ea57bSMasahiro Yamada 123fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 124fe5ea57bSMasahiro Yamada ldr r1, [r0] 125fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 126fe5ea57bSMasahiro Yamada str r1, [r0] 127fe5ea57bSMasahiro Yamada 128ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE) 129fe5ea57bSMasahiro Yamada 130fe5ea57bSMasahiro Yamada b init_uart 131*5b660066SMasahiro Yamadapxs2_end: 132fe5ea57bSMasahiro Yamada#endif 133ea65c980SMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_LD6B) 134ea65c980SMasahiro Yamada#define UNIPHIER_LD6B_UART_CLK 88900000 135fe5ea57bSMasahiro Yamada cmp r1, #0x2F 136*5b660066SMasahiro Yamada bne ld6b_end 137fe5ea57bSMasahiro Yamada 138fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 139fe5ea57bSMasahiro Yamada ldr r1, [r0] 140fe5ea57bSMasahiro Yamada orr r1, r1, #1 141fe5ea57bSMasahiro Yamada str r1, [r0] 142fe5ea57bSMasahiro Yamada 143fe5ea57bSMasahiro Yamada sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0 144fe5ea57bSMasahiro Yamada sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 145fe5ea57bSMasahiro Yamada sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 146fe5ea57bSMasahiro Yamada 147fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 148fe5ea57bSMasahiro Yamada ldr r1, [r0] 149fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 150fe5ea57bSMasahiro Yamada str r1, [r0] 151fe5ea57bSMasahiro Yamada 152ea65c980SMasahiro Yamada ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE) 153fe5ea57bSMasahiro Yamada 154fe5ea57bSMasahiro Yamada b init_uart 155*5b660066SMasahiro Yamadald6b_end: 156fe5ea57bSMasahiro Yamada#endif 1575d076486SMasahiro Yamada mov pc, lr 158fe5ea57bSMasahiro Yamada 159fe5ea57bSMasahiro Yamadainit_uart: 160fe5ea57bSMasahiro Yamada addruart r0, r1, r2 161fe5ea57bSMasahiro Yamada mov r1, #UART_LCR_WLEN8 << 8 162fe5ea57bSMasahiro Yamada str r1, [r0, #0x10] 163fe5ea57bSMasahiro Yamada str r3, [r0, #0x24] 164fe5ea57bSMasahiro Yamada 165fe5ea57bSMasahiro Yamada mov pc, lr 166fe5ea57bSMasahiro YamadaENDPROC(debug_ll_init) 167