1c474a8ebSMinkyu Kang/* 2c474a8ebSMinkyu Kang * Memory Setup stuff - taken from blob memsetup.S 3c474a8ebSMinkyu Kang * 4c474a8ebSMinkyu Kang * Copyright (C) 2009 Samsung Electronics 5c474a8ebSMinkyu Kang * Kyungmin Park <kyungmin.park@samsung.com> 6c474a8ebSMinkyu Kang * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8c474a8ebSMinkyu Kang */ 9c474a8ebSMinkyu Kang 10c474a8ebSMinkyu Kang#include <config.h> 11c474a8ebSMinkyu Kang#include <asm/arch/cpu.h> 12c474a8ebSMinkyu Kang#include <asm/arch/clock.h> 13c474a8ebSMinkyu Kang#include <asm/arch/power.h> 14c474a8ebSMinkyu Kang 15c474a8ebSMinkyu Kang/* 16c474a8ebSMinkyu Kang * Register usages: 17c474a8ebSMinkyu Kang * 18c474a8ebSMinkyu Kang * r5 has zero always 19c474a8ebSMinkyu Kang * r7 has S5PC100 GPIO base, 0xE0300000 20c474a8ebSMinkyu Kang * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively 21c474a8ebSMinkyu Kang * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on 22c474a8ebSMinkyu Kang */ 23c474a8ebSMinkyu Kang 24c474a8ebSMinkyu Kang .globl lowlevel_init 25c474a8ebSMinkyu Kanglowlevel_init: 26c474a8ebSMinkyu Kang mov r11, lr 27c474a8ebSMinkyu Kang 28c474a8ebSMinkyu Kang /* r5 has always zero */ 29c474a8ebSMinkyu Kang mov r5, #0 30c474a8ebSMinkyu Kang 31c474a8ebSMinkyu Kang ldr r7, =S5PC100_GPIO_BASE 32c474a8ebSMinkyu Kang ldr r8, =S5PC100_GPIO_BASE 33c474a8ebSMinkyu Kang /* Read CPU ID */ 34d93d0f0cSMinkyu Kang ldr r2, =S5PC110_PRO_ID 35c474a8ebSMinkyu Kang ldr r0, [r2] 36c474a8ebSMinkyu Kang mov r1, #0x00010000 37c474a8ebSMinkyu Kang and r0, r0, r1 38c474a8ebSMinkyu Kang cmp r0, r5 39c474a8ebSMinkyu Kang beq 100f 40c474a8ebSMinkyu Kang ldr r8, =S5PC110_GPIO_BASE 41c474a8ebSMinkyu Kang100: 42c474a8ebSMinkyu Kang /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ 43c474a8ebSMinkyu Kang cmp r7, r8 44c474a8ebSMinkyu Kang beq skip_check_didle @ Support C110 only 45c474a8ebSMinkyu Kang 46c474a8ebSMinkyu Kang ldr r0, =S5PC110_RST_STAT 47c474a8ebSMinkyu Kang ldr r1, [r0] 48c474a8ebSMinkyu Kang and r1, r1, #0x000D0000 49c474a8ebSMinkyu Kang cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP 50c474a8ebSMinkyu Kang beq didle_wakeup 51c474a8ebSMinkyu Kang cmp r7, r8 52c474a8ebSMinkyu Kang 53c474a8ebSMinkyu Kangskip_check_didle: 54c474a8ebSMinkyu Kang addeq r0, r8, #0x280 @ S5PC100_GPIO_J4 55c474a8ebSMinkyu Kang addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4 56c474a8ebSMinkyu Kang ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET 57c474a8ebSMinkyu Kang bic r1, r1, #(0xf << 4) @ 1 * 4-bit 58c474a8ebSMinkyu Kang orr r1, r1, #(0x1 << 4) 59c474a8ebSMinkyu Kang str r1, [r0, #0x0] @ GPIO_CON_OFFSET 60c474a8ebSMinkyu Kang 61c474a8ebSMinkyu Kang ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET 62c474a8ebSMinkyu Kang bic r1, r1, #(1 << 1) 63c474a8ebSMinkyu Kang str r1, [r0, #0x4] @ GPIO_DAT_OFFSET 64c474a8ebSMinkyu Kang 65c474a8ebSMinkyu Kang /* Don't setup at s5pc100 */ 66c474a8ebSMinkyu Kang beq 100f 67c474a8ebSMinkyu Kang 68c474a8ebSMinkyu Kang /* 69c474a8ebSMinkyu Kang * Initialize Async Register Setting for EVT1 70c474a8ebSMinkyu Kang * Because we are setting EVT1 as the default value of EVT0, 71c474a8ebSMinkyu Kang * setting EVT0 as well does not make things worse. 72c474a8ebSMinkyu Kang * Thus, for the simplicity, we set for EVT0, too 73c474a8ebSMinkyu Kang * 74c474a8ebSMinkyu Kang * The "Async Registers" are: 75c474a8ebSMinkyu Kang * 0xE0F0_0000 76c474a8ebSMinkyu Kang * 0xE1F0_0000 77c474a8ebSMinkyu Kang * 0xF180_0000 78c474a8ebSMinkyu Kang * 0xF190_0000 79c474a8ebSMinkyu Kang * 0xF1A0_0000 80c474a8ebSMinkyu Kang * 0xF1B0_0000 81c474a8ebSMinkyu Kang * 0xF1C0_0000 82c474a8ebSMinkyu Kang * 0xF1D0_0000 83c474a8ebSMinkyu Kang * 0xF1E0_0000 84c474a8ebSMinkyu Kang * 0xF1F0_0000 85c474a8ebSMinkyu Kang * 0xFAF0_0000 86c474a8ebSMinkyu Kang */ 87c474a8ebSMinkyu Kang ldr r0, =0xe0f00000 88c474a8ebSMinkyu Kang ldr r1, [r0] 89c474a8ebSMinkyu Kang bic r1, r1, #0x1 90c474a8ebSMinkyu Kang str r1, [r0] 91c474a8ebSMinkyu Kang 92c474a8ebSMinkyu Kang ldr r0, =0xe1f00000 93c474a8ebSMinkyu Kang ldr r1, [r0] 94c474a8ebSMinkyu Kang bic r1, r1, #0x1 95c474a8ebSMinkyu Kang str r1, [r0] 96c474a8ebSMinkyu Kang 97c474a8ebSMinkyu Kang ldr r0, =0xf1800000 98c474a8ebSMinkyu Kang ldr r1, [r0] 99c474a8ebSMinkyu Kang bic r1, r1, #0x1 100c474a8ebSMinkyu Kang str r1, [r0] 101c474a8ebSMinkyu Kang 102c474a8ebSMinkyu Kang ldr r0, =0xf1900000 103c474a8ebSMinkyu Kang ldr r1, [r0] 104c474a8ebSMinkyu Kang bic r1, r1, #0x1 105c474a8ebSMinkyu Kang str r1, [r0] 106c474a8ebSMinkyu Kang 107c474a8ebSMinkyu Kang ldr r0, =0xf1a00000 108c474a8ebSMinkyu Kang ldr r1, [r0] 109c474a8ebSMinkyu Kang bic r1, r1, #0x1 110c474a8ebSMinkyu Kang str r1, [r0] 111c474a8ebSMinkyu Kang 112c474a8ebSMinkyu Kang ldr r0, =0xf1b00000 113c474a8ebSMinkyu Kang ldr r1, [r0] 114c474a8ebSMinkyu Kang bic r1, r1, #0x1 115c474a8ebSMinkyu Kang str r1, [r0] 116c474a8ebSMinkyu Kang 117c474a8ebSMinkyu Kang ldr r0, =0xf1c00000 118c474a8ebSMinkyu Kang ldr r1, [r0] 119c474a8ebSMinkyu Kang bic r1, r1, #0x1 120c474a8ebSMinkyu Kang str r1, [r0] 121c474a8ebSMinkyu Kang 122c474a8ebSMinkyu Kang ldr r0, =0xf1d00000 123c474a8ebSMinkyu Kang ldr r1, [r0] 124c474a8ebSMinkyu Kang bic r1, r1, #0x1 125c474a8ebSMinkyu Kang str r1, [r0] 126c474a8ebSMinkyu Kang 127c474a8ebSMinkyu Kang ldr r0, =0xf1e00000 128c474a8ebSMinkyu Kang ldr r1, [r0] 129c474a8ebSMinkyu Kang bic r1, r1, #0x1 130c474a8ebSMinkyu Kang str r1, [r0] 131c474a8ebSMinkyu Kang 132c474a8ebSMinkyu Kang ldr r0, =0xf1f00000 133c474a8ebSMinkyu Kang ldr r1, [r0] 134c474a8ebSMinkyu Kang bic r1, r1, #0x1 135c474a8ebSMinkyu Kang str r1, [r0] 136c474a8ebSMinkyu Kang 137c474a8ebSMinkyu Kang ldr r0, =0xfaf00000 138c474a8ebSMinkyu Kang ldr r1, [r0] 139c474a8ebSMinkyu Kang bic r1, r1, #0x1 140c474a8ebSMinkyu Kang str r1, [r0] 141c474a8ebSMinkyu Kang 142c474a8ebSMinkyu Kang /* 143c474a8ebSMinkyu Kang * Diable ABB block to reduce sleep current at low temperature 144c474a8ebSMinkyu Kang * Note that it's hidden register setup don't modify it 145c474a8ebSMinkyu Kang */ 146c474a8ebSMinkyu Kang ldr r0, =0xE010C300 147c474a8ebSMinkyu Kang ldr r1, =0x00800000 148c474a8ebSMinkyu Kang str r1, [r0] 149c474a8ebSMinkyu Kang 150c474a8ebSMinkyu Kang100: 151c474a8ebSMinkyu Kang /* IO retension release */ 152c474a8ebSMinkyu Kang ldreq r0, =S5PC100_OTHERS @ 0xE0108200 153c474a8ebSMinkyu Kang ldrne r0, =S5PC110_OTHERS @ 0xE010E000 154c474a8ebSMinkyu Kang ldr r1, [r0] 155c474a8ebSMinkyu Kang ldreq r2, =(1 << 31) @ IO_RET_REL 156c474a8ebSMinkyu Kang ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) 157c474a8ebSMinkyu Kang orr r1, r1, r2 158c474a8ebSMinkyu Kang /* Do not release retention here for S5PC110 */ 159c474a8ebSMinkyu Kang streq r1, [r0] 160c474a8ebSMinkyu Kang 161c474a8ebSMinkyu Kang /* Disable Watchdog */ 162c474a8ebSMinkyu Kang ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 163c474a8ebSMinkyu Kang ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 164c474a8ebSMinkyu Kang str r5, [r0] 165c474a8ebSMinkyu Kang 166c474a8ebSMinkyu Kang /* setting SRAM */ 167c474a8ebSMinkyu Kang ldreq r0, =S5PC100_SROMC_BASE 168c474a8ebSMinkyu Kang ldrne r0, =S5PC110_SROMC_BASE 169c474a8ebSMinkyu Kang ldr r1, =0x9 170c474a8ebSMinkyu Kang str r1, [r0] 171c474a8ebSMinkyu Kang 172c474a8ebSMinkyu Kang /* S5PC100 has 3 groups of interrupt sources */ 173c474a8ebSMinkyu Kang ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 174c474a8ebSMinkyu Kang ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000 175c474a8ebSMinkyu Kang add r1, r0, #0x00100000 176c474a8ebSMinkyu Kang add r2, r0, #0x00200000 177c474a8ebSMinkyu Kang 178c474a8ebSMinkyu Kang /* Disable all interrupts (VIC0, VIC1 and VIC2) */ 179c474a8ebSMinkyu Kang mvn r3, #0x0 180c474a8ebSMinkyu Kang str r3, [r0, #0x14] @ INTENCLEAR 181c474a8ebSMinkyu Kang str r3, [r1, #0x14] @ INTENCLEAR 182c474a8ebSMinkyu Kang str r3, [r2, #0x14] @ INTENCLEAR 183c474a8ebSMinkyu Kang 184c474a8ebSMinkyu Kang /* Set all interrupts as IRQ */ 185c474a8ebSMinkyu Kang str r5, [r0, #0xc] @ INTSELECT 186c474a8ebSMinkyu Kang str r5, [r1, #0xc] @ INTSELECT 187c474a8ebSMinkyu Kang str r5, [r2, #0xc] @ INTSELECT 188c474a8ebSMinkyu Kang 189c474a8ebSMinkyu Kang /* Pending Interrupt Clear */ 190c474a8ebSMinkyu Kang str r5, [r0, #0xf00] @ INTADDRESS 191c474a8ebSMinkyu Kang str r5, [r1, #0xf00] @ INTADDRESS 192c474a8ebSMinkyu Kang str r5, [r2, #0xf00] @ INTADDRESS 193c474a8ebSMinkyu Kang 194c474a8ebSMinkyu Kang /* for UART */ 195c474a8ebSMinkyu Kang bl uart_asm_init 196c474a8ebSMinkyu Kang 197c474a8ebSMinkyu Kang bl internal_ram_init 198c474a8ebSMinkyu Kang 199c474a8ebSMinkyu Kang cmp r7, r8 200c474a8ebSMinkyu Kang /* Clear wakeup status register */ 201c474a8ebSMinkyu Kang ldreq r0, =S5PC100_WAKEUP_STAT 202c474a8ebSMinkyu Kang ldrne r0, =S5PC110_WAKEUP_STAT 203c474a8ebSMinkyu Kang ldr r1, [r0] 204c474a8ebSMinkyu Kang str r1, [r0] 205c474a8ebSMinkyu Kang 206c474a8ebSMinkyu Kang /* IO retension release */ 207c474a8ebSMinkyu Kang ldreq r0, =S5PC100_OTHERS @ 0xE0108200 208c474a8ebSMinkyu Kang ldrne r0, =S5PC110_OTHERS @ 0xE010E000 209c474a8ebSMinkyu Kang ldr r1, [r0] 210c474a8ebSMinkyu Kang ldreq r2, =(1 << 31) @ IO_RET_REL 211c474a8ebSMinkyu Kang ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) 212c474a8ebSMinkyu Kang orr r1, r1, r2 213c474a8ebSMinkyu Kang str r1, [r0] 214c474a8ebSMinkyu Kang 215c474a8ebSMinkyu Kang b 1f 216c474a8ebSMinkyu Kang 217c474a8ebSMinkyu Kangdidle_wakeup: 218c474a8ebSMinkyu Kang /* Wait when APLL is locked */ 219c474a8ebSMinkyu Kang ldr r0, =0xE0100100 @ S5PC110_APLL_CON 220c474a8ebSMinkyu Kanglockloop: 221c474a8ebSMinkyu Kang ldr r1, [r0] 222c474a8ebSMinkyu Kang and r1, r1, #(1 << 29) 223c474a8ebSMinkyu Kang cmp r1, #(1 << 29) 224c474a8ebSMinkyu Kang bne lockloop 225c474a8ebSMinkyu Kang 226c474a8ebSMinkyu Kang ldr r0, =S5PC110_INFORM0 227c474a8ebSMinkyu Kang ldr r1, [r0] 228c474a8ebSMinkyu Kang mov pc, r1 229c474a8ebSMinkyu Kang nop 230c474a8ebSMinkyu Kang nop 231c474a8ebSMinkyu Kang nop 232c474a8ebSMinkyu Kang nop 233c474a8ebSMinkyu Kang nop 234c474a8ebSMinkyu Kang 235c474a8ebSMinkyu Kang1: 236c474a8ebSMinkyu Kang mov lr, r11 237c474a8ebSMinkyu Kang mov pc, lr 238c474a8ebSMinkyu Kang 239c474a8ebSMinkyu Kang/* 240c474a8ebSMinkyu Kang * system_clock_init: Initialize core clock and bus clock. 241c474a8ebSMinkyu Kang * void system_clock_init(void) 242c474a8ebSMinkyu Kang */ 243c474a8ebSMinkyu Kangsystem_clock_init: 244d93d0f0cSMinkyu Kang ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 245c474a8ebSMinkyu Kang 246c474a8ebSMinkyu Kang /* Check S5PC100 */ 247c474a8ebSMinkyu Kang cmp r7, r8 248c474a8ebSMinkyu Kang bne 110f 249c474a8ebSMinkyu Kang100: 250c474a8ebSMinkyu Kang /* Set Lock Time */ 251c474a8ebSMinkyu Kang ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 252c474a8ebSMinkyu Kang str r1, [r0, #0x000] @ S5PC100_APLL_LOCK 253c474a8ebSMinkyu Kang str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK 254c474a8ebSMinkyu Kang str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK 255c474a8ebSMinkyu Kang str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK 256c474a8ebSMinkyu Kang 257c474a8ebSMinkyu Kang /* S5P_APLL_CON */ 258c474a8ebSMinkyu Kang ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) 259c474a8ebSMinkyu Kang str r1, [r0, #0x100] 260c474a8ebSMinkyu Kang /* S5P_MPLL_CON */ 261c474a8ebSMinkyu Kang ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) 262c474a8ebSMinkyu Kang str r1, [r0, #0x104] 263c474a8ebSMinkyu Kang /* S5P_EPLL_CON */ 264c474a8ebSMinkyu Kang ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) 265c474a8ebSMinkyu Kang str r1, [r0, #0x108] 266c474a8ebSMinkyu Kang /* S5P_HPLL_CON */ 267c474a8ebSMinkyu Kang ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 268c474a8ebSMinkyu Kang str r1, [r0, #0x10C] 269c474a8ebSMinkyu Kang 270c474a8ebSMinkyu Kang ldr r1, [r0, #0x300] 271c474a8ebSMinkyu Kang ldr r2, =0x00003fff 272c474a8ebSMinkyu Kang bic r1, r1, r2 273c474a8ebSMinkyu Kang ldr r2, =0x00011301 274c474a8ebSMinkyu Kang 275c474a8ebSMinkyu Kang orr r1, r1, r2 276c474a8ebSMinkyu Kang str r1, [r0, #0x300] 277c474a8ebSMinkyu Kang ldr r1, [r0, #0x304] 278c474a8ebSMinkyu Kang ldr r2, =0x00011110 279c474a8ebSMinkyu Kang orr r1, r1, r2 280c474a8ebSMinkyu Kang str r1, [r0, #0x304] 281c474a8ebSMinkyu Kang ldr r1, =0x00000001 282c474a8ebSMinkyu Kang str r1, [r0, #0x308] 283c474a8ebSMinkyu Kang 284c474a8ebSMinkyu Kang /* Set Source Clock */ 285c474a8ebSMinkyu Kang ldr r1, =0x00001111 @ A, M, E, HPLL Muxing 286c474a8ebSMinkyu Kang str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 287c474a8ebSMinkyu Kang 288c474a8ebSMinkyu Kang b 200f 289c474a8ebSMinkyu Kang110: 290c474a8ebSMinkyu Kang ldr r0, =0xE010C000 @ S5PC110_PWR_CFG 291c474a8ebSMinkyu Kang 292c474a8ebSMinkyu Kang /* Set OSC_FREQ value */ 293c474a8ebSMinkyu Kang ldr r1, =0xf 294c474a8ebSMinkyu Kang str r1, [r0, #0x100] @ S5PC110_OSC_FREQ 295c474a8ebSMinkyu Kang 296c474a8ebSMinkyu Kang /* Set MTC_STABLE value */ 297c474a8ebSMinkyu Kang ldr r1, =0xffffffff 298c474a8ebSMinkyu Kang str r1, [r0, #0x110] @ S5PC110_MTC_STABLE 299c474a8ebSMinkyu Kang 300c474a8ebSMinkyu Kang /* Set CLAMP_STABLE value */ 301c474a8ebSMinkyu Kang ldr r1, =0x3ff03ff 302c474a8ebSMinkyu Kang str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE 303c474a8ebSMinkyu Kang 304d93d0f0cSMinkyu Kang ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 305c474a8ebSMinkyu Kang 306c474a8ebSMinkyu Kang /* Set Clock divider */ 307c474a8ebSMinkyu Kang ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 308c474a8ebSMinkyu Kang str r1, [r0, #0x300] 309c474a8ebSMinkyu Kang ldr r1, =0x11110111 @ UART[3210]: MMC[3210] 310c474a8ebSMinkyu Kang str r1, [r0, #0x310] 311c474a8ebSMinkyu Kang 312c474a8ebSMinkyu Kang /* Set Lock Time */ 313c474a8ebSMinkyu Kang ldr r1, =0x2cf @ Locktime : 30us 314c474a8ebSMinkyu Kang str r1, [r0, #0x000] @ S5PC110_APLL_LOCK 315c474a8ebSMinkyu Kang ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 316c474a8ebSMinkyu Kang str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK 317c474a8ebSMinkyu Kang str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK 318c474a8ebSMinkyu Kang str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK 319c474a8ebSMinkyu Kang 320c474a8ebSMinkyu Kang /* S5PC110_APLL_CON */ 321c474a8ebSMinkyu Kang ldr r1, =0x80C80601 @ 800MHz 322c474a8ebSMinkyu Kang str r1, [r0, #0x100] 323c474a8ebSMinkyu Kang /* S5PC110_MPLL_CON */ 324c474a8ebSMinkyu Kang ldr r1, =0x829B0C01 @ 667MHz 325c474a8ebSMinkyu Kang str r1, [r0, #0x108] 326c474a8ebSMinkyu Kang /* S5PC110_EPLL_CON */ 327c474a8ebSMinkyu Kang ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2 328c474a8ebSMinkyu Kang str r1, [r0, #0x110] 329c474a8ebSMinkyu Kang /* S5PC110_VPLL_CON */ 330c474a8ebSMinkyu Kang ldr r1, =0x806C0603 @ 54MHz 331c474a8ebSMinkyu Kang str r1, [r0, #0x120] 332c474a8ebSMinkyu Kang 333c474a8ebSMinkyu Kang /* Set Source Clock */ 334c474a8ebSMinkyu Kang ldr r1, =0x10001111 @ A, M, E, VPLL Muxing 335c474a8ebSMinkyu Kang str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 336c474a8ebSMinkyu Kang 337c474a8ebSMinkyu Kang /* OneDRAM(DMC0) clock setting */ 338c474a8ebSMinkyu Kang ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL 339c474a8ebSMinkyu Kang str r1, [r0, #0x218] @ S5PC110_CLK_SRC6 340c474a8ebSMinkyu Kang ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1 341c474a8ebSMinkyu Kang str r1, [r0, #0x318] @ S5PC110_CLK_DIV6 342c474a8ebSMinkyu Kang 343c474a8ebSMinkyu Kang /* XCLKOUT = XUSBXTI 24MHz */ 344c474a8ebSMinkyu Kang add r2, r0, #0xE000 @ S5PC110_OTHERS 345c474a8ebSMinkyu Kang ldr r1, [r2] 346c474a8ebSMinkyu Kang orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI 347c474a8ebSMinkyu Kang str r1, [r2] 348c474a8ebSMinkyu Kang 349c474a8ebSMinkyu Kang /* CLK_IP0 */ 350c474a8ebSMinkyu Kang ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5] 351c474a8ebSMinkyu Kang str r1, [r0, #0x460] @ S5PC110_CLK_IP0 352c474a8ebSMinkyu Kang 353c474a8ebSMinkyu Kang /* CLK_IP1 */ 354c474a8ebSMinkyu Kang ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16] 355c474a8ebSMinkyu Kang @ NANDXL[24] 356c474a8ebSMinkyu Kang str r1, [r0, #0x464] @ S5PC110_CLK_IP1 357c474a8ebSMinkyu Kang 358c474a8ebSMinkyu Kang /* CLK_IP2 */ 359c474a8ebSMinkyu Kang ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9] 360c474a8ebSMinkyu Kang @ HOSTIF[10] HSMMC0[16] 361c474a8ebSMinkyu Kang @ HSMMC2[18] VIC[27:24] 362c474a8ebSMinkyu Kang str r1, [r0, #0x468] @ S5PC110_CLK_IP2 363c474a8ebSMinkyu Kang 364c474a8ebSMinkyu Kang /* CLK_IP3 */ 365c474a8ebSMinkyu Kang ldr r1, =0x8eff038c @ I2C[8:6] 366c474a8ebSMinkyu Kang @ SYSTIMER[16] UART0[17] 367c474a8ebSMinkyu Kang @ UART1[18] UART2[19] 368c474a8ebSMinkyu Kang @ UART3[20] WDT[22] 369c474a8ebSMinkyu Kang @ PWM[23] GPIO[26] SYSCON[27] 370c474a8ebSMinkyu Kang str r1, [r0, #0x46c] @ S5PC110_CLK_IP3 371c474a8ebSMinkyu Kang 372c474a8ebSMinkyu Kang /* CLK_IP4 */ 373c474a8ebSMinkyu Kang ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5] 374c474a8ebSMinkyu Kang str r1, [r0, #0x470] @ S5PC110_CLK_IP3 375c474a8ebSMinkyu Kang 376c474a8ebSMinkyu Kang200: 377c474a8ebSMinkyu Kang /* wait at least 200us to stablize all clock */ 378c474a8ebSMinkyu Kang mov r2, #0x10000 379c474a8ebSMinkyu Kang1: subs r2, r2, #1 380c474a8ebSMinkyu Kang bne 1b 381c474a8ebSMinkyu Kang 382c474a8ebSMinkyu Kang mov pc, lr 383c474a8ebSMinkyu Kang 384c474a8ebSMinkyu Kanginternal_ram_init: 385c474a8ebSMinkyu Kang ldreq r0, =0xE3800000 386c474a8ebSMinkyu Kang ldrne r0, =0xF1500000 387c474a8ebSMinkyu Kang ldr r1, =0x0 388c474a8ebSMinkyu Kang str r1, [r0] 389c474a8ebSMinkyu Kang 390c474a8ebSMinkyu Kang mov pc, lr 391c474a8ebSMinkyu Kang 392c474a8ebSMinkyu Kang/* 393c474a8ebSMinkyu Kang * uart_asm_init: Initialize UART's pins 394c474a8ebSMinkyu Kang */ 395c474a8ebSMinkyu Kanguart_asm_init: 396c474a8ebSMinkyu Kang /* set GPIO to enable UART0-UART4 */ 397c474a8ebSMinkyu Kang mov r0, r8 398c474a8ebSMinkyu Kang ldr r1, =0x22222222 399c474a8ebSMinkyu Kang str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET 400c474a8ebSMinkyu Kang ldr r1, =0x00002222 401c474a8ebSMinkyu Kang str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET 402c474a8ebSMinkyu Kang 403c474a8ebSMinkyu Kang /* Check S5PC100 */ 404c474a8ebSMinkyu Kang cmp r7, r8 405c474a8ebSMinkyu Kang bne 110f 406c474a8ebSMinkyu Kang 407c474a8ebSMinkyu Kang /* UART_SEL GPK0[5] at S5PC100 */ 408c474a8ebSMinkyu Kang add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET 409c474a8ebSMinkyu Kang ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET 410c474a8ebSMinkyu Kang bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit 411c474a8ebSMinkyu Kang orr r1, r1, #(0x1 << 20) @ Output 412c474a8ebSMinkyu Kang str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET 413c474a8ebSMinkyu Kang 414c474a8ebSMinkyu Kang ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET 415c474a8ebSMinkyu Kang bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit 416c474a8ebSMinkyu Kang orr r1, r1, #(0x2 << 10) @ Pull-up enabled 417c474a8ebSMinkyu Kang str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET 418c474a8ebSMinkyu Kang 419c474a8ebSMinkyu Kang ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 420c474a8ebSMinkyu Kang orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit 421c474a8ebSMinkyu Kang str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 422c474a8ebSMinkyu Kang 423c474a8ebSMinkyu Kang b 200f 424c474a8ebSMinkyu Kang110: 425c474a8ebSMinkyu Kang /* 426c474a8ebSMinkyu Kang * Note that the following address 427c474a8ebSMinkyu Kang * 0xE020'0360 is reserved address at S5PC100 428c474a8ebSMinkyu Kang */ 429c474a8ebSMinkyu Kang /* UART_SEL MP0_5[7] at S5PC110 */ 430c474a8ebSMinkyu Kang add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET 431c474a8ebSMinkyu Kang ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET 432c474a8ebSMinkyu Kang bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit 433c474a8ebSMinkyu Kang orr r1, r1, #(0x1 << 28) @ Output 434c474a8ebSMinkyu Kang str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET 435c474a8ebSMinkyu Kang 436c474a8ebSMinkyu Kang ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET 437c474a8ebSMinkyu Kang bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit 438c474a8ebSMinkyu Kang orr r1, r1, #(0x2 << 14) @ Pull-up enabled 439c474a8ebSMinkyu Kang str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET 440c474a8ebSMinkyu Kang 441c474a8ebSMinkyu Kang ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 442c474a8ebSMinkyu Kang orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit 443c474a8ebSMinkyu Kang str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 444c474a8ebSMinkyu Kang200: 445c474a8ebSMinkyu Kang mov pc, lr 446