Lines Matching refs:ldr

22 	ldr \tmp, =IIM_BASE_ADDR
23 	ldr \ret, [\tmp, #IIM_SREV]
33 	ldr r0, =DBG_BASE_ADDR
34 	ldr r1, =DBG_CSCR_U_CONFIG
36 	ldr r1, =DBG_CSCR_L_CONFIG
38 	ldr r1, =DBG_CSCR_A_CONFIG
44 	ldr r0, =CCM_BASE_ADDR
47 	ldr r1, [r0, #CLKCTL_COSR]
55 	ldr r2, =CCM_CCMR_CONFIG
62 	ldr r2, [r0, #CLKCTL_PDR0]
69 	ldr r1, =CCM_PPLL_300_HZ
72 	ldr r1, =CCM_PDR0_CONFIG
76 	ldr r1, [r0, #CLKCTL_CGR0]
80 	ldr r1, [r0, #CLKCTL_CGR1]
85 	ldr r1, [r0, #CLKCTL_CGR2]
91 	ldr r0, =ESDCTL_BASE_ADDR
112 	ldr r3, =ESDCTL_DELAY_LINE5
169 	ldr r3, =ESDCTL_0x92220000
173 	ldr r4, =ESDCTL_PRECHARGE
180 	ldr r3, =ESDCTL_0xB2220000
184 	ldr r4, =ESDCTL_DDR2_EMR2
186 	ldr r4, =ESDCTL_DDR2_EMR3
188 	ldr r4, =ESDCTL_DDR2_EN_DLL
190 	ldr r4, =ESDCTL_DDR2_RESET_DLL
193 	ldr r3, =ESDCTL_0x92220000
197 	ldr r4, =ESDCTL_PRECHARGE
202 	ldr r3, =ESDCTL_0xA2220000
209 	ldr r3, =ESDCTL_0xB2220000
224 	ldr r3, =ESDCTL_0x82228080
235 	ldr r4, [r1, #0x100]