1*bcc05c7aStrem/* 2*bcc05c7aStrem * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr> 3*bcc05c7aStrem * 4*bcc05c7aStrem * SPDX-License-Identifier: GPL-2.0+ 5*bcc05c7aStrem */ 6*bcc05c7aStrem 7*bcc05c7aStrem#include <config.h> 8*bcc05c7aStrem#include <generated/asm-offsets.h> 9*bcc05c7aStrem#include <asm/macro.h> 10*bcc05c7aStrem#include <asm/arch/imx-regs.h> 11*bcc05c7aStrem#include "apf27.h" 12*bcc05c7aStrem 13*bcc05c7aStrem .macro init_aipi 14*bcc05c7aStrem /* 15*bcc05c7aStrem * setup AIPI1 and AIPI2 16*bcc05c7aStrem */ 17*bcc05c7aStrem write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL 18*bcc05c7aStrem write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL 19*bcc05c7aStrem write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL 20*bcc05c7aStrem write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL 21*bcc05c7aStrem 22*bcc05c7aStrem /* Change SDRAM signal strengh */ 23*bcc05c7aStrem ldr r0, =GPCR 24*bcc05c7aStrem ldr r1, =ACFG_GPCR_VAL 25*bcc05c7aStrem ldr r5, [r0] 26*bcc05c7aStrem orr r5, r5, r1 27*bcc05c7aStrem str r5, [r0] 28*bcc05c7aStrem 29*bcc05c7aStrem .endm /* init_aipi */ 30*bcc05c7aStrem 31*bcc05c7aStrem .macro init_clock 32*bcc05c7aStrem ldr r0, =CSCR 33*bcc05c7aStrem /* disable MPLL/SPLL first */ 34*bcc05c7aStrem ldr r1, [r0] 35*bcc05c7aStrem bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) 36*bcc05c7aStrem str r1, [r0] 37*bcc05c7aStrem 38*bcc05c7aStrem /* 39*bcc05c7aStrem * pll clock initialization predefined in apf27.h 40*bcc05c7aStrem */ 41*bcc05c7aStrem write32 MPCTL0, ACFG_MPCTL0_VAL 42*bcc05c7aStrem write32 SPCTL0, ACFG_SPCTL0_VAL 43*bcc05c7aStrem 44*bcc05c7aStrem write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART 45*bcc05c7aStrem 46*bcc05c7aStrem /* 47*bcc05c7aStrem * add some delay here 48*bcc05c7aStrem */ 49*bcc05c7aStrem mov r1, #0x1000 50*bcc05c7aStrem 1: subs r1, r1, #0x1 51*bcc05c7aStrem bne 1b 52*bcc05c7aStrem 53*bcc05c7aStrem /* peripheral clock divider */ 54*bcc05c7aStrem write32 PCDR0, ACFG_PCDR0_VAL 55*bcc05c7aStrem write32 PCDR1, ACFG_PCDR1_VAL 56*bcc05c7aStrem 57*bcc05c7aStrem /* Configure PCCR0 and PCCR1 */ 58*bcc05c7aStrem write32 PCCR0, ACFG_PCCR0_VAL 59*bcc05c7aStrem write32 PCCR1, ACFG_PCCR1_VAL 60*bcc05c7aStrem 61*bcc05c7aStrem .endm /* init_clock */ 62*bcc05c7aStrem 63*bcc05c7aStrem .macro init_ddr 64*bcc05c7aStrem /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ 65*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 66*bcc05c7aStrem ldr r4, =ESDMISC_SDRAM_RDY 67*bcc05c7aStrem2: ldr r1, [r0, #ESDMISC_ROF] 68*bcc05c7aStrem ands r1, r1, r4 69*bcc05c7aStrem bpl 2b 70*bcc05c7aStrem 71*bcc05c7aStrem /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ 72*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 73*bcc05c7aStrem ldr r4, =ACFG_ESDMISC_VAL 74*bcc05c7aStrem orr r1, r4, #ESDMISC_MDDR_DL_RST 75*bcc05c7aStrem str r1, [r0, #ESDMISC_ROF] 76*bcc05c7aStrem 77*bcc05c7aStrem /* Hold for more than 200ns */ 78*bcc05c7aStrem ldr r1, =0x10000 79*bcc05c7aStrem1: subs r1, r1, #0x1 80*bcc05c7aStrem bne 1b 81*bcc05c7aStrem 82*bcc05c7aStrem str r4, [r0] 83*bcc05c7aStrem 84*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 85*bcc05c7aStrem ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 86*bcc05c7aStrem str r1, [r0, #ESDCFG0_ROF] 87*bcc05c7aStrem 88*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 89*bcc05c7aStrem ldr r1, =ACFG_PRECHARGE_CMD 90*bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 91*bcc05c7aStrem 92*bcc05c7aStrem /* write8(0xA0001000, any value) */ 93*bcc05c7aStrem ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL 94*bcc05c7aStrem strb r2, [r1] 95*bcc05c7aStrem 96*bcc05c7aStrem ldr r1, =ACFG_AUTOREFRESH_CMD 97*bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 98*bcc05c7aStrem 99*bcc05c7aStrem ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ 100*bcc05c7aStrem 101*bcc05c7aStrem ldr r6,=0x7 /* load loop counter */ 102*bcc05c7aStrem1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 103*bcc05c7aStrem subs r6,r6,#1 104*bcc05c7aStrem bne 1b 105*bcc05c7aStrem 106*bcc05c7aStrem ldr r1, =ACFG_SET_MODE_REG_CMD 107*bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 108*bcc05c7aStrem 109*bcc05c7aStrem /* set standard mode register */ 110*bcc05c7aStrem ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL 111*bcc05c7aStrem strb r2, [r4] 112*bcc05c7aStrem 113*bcc05c7aStrem /* set extended mode register */ 114*bcc05c7aStrem ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 115*bcc05c7aStrem strb r5, [r4] 116*bcc05c7aStrem 117*bcc05c7aStrem ldr r1, =ACFG_NORMAL_RW_CMD 118*bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 119*bcc05c7aStrem 120*bcc05c7aStrem /* 2nd sdram */ 121*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 122*bcc05c7aStrem ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 123*bcc05c7aStrem str r1, [r0, #ESDCFG1_ROF] 124*bcc05c7aStrem 125*bcc05c7aStrem ldr r0, =IMX_ESD_BASE 126*bcc05c7aStrem ldr r1, =ACFG_PRECHARGE_CMD 127*bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 128*bcc05c7aStrem 129*bcc05c7aStrem /* write8(0xB0001000, any value) */ 130*bcc05c7aStrem ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL 131*bcc05c7aStrem strb r2, [r1] 132*bcc05c7aStrem 133*bcc05c7aStrem ldr r1, =ACFG_AUTOREFRESH_CMD 134*bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 135*bcc05c7aStrem 136*bcc05c7aStrem ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ 137*bcc05c7aStrem 138*bcc05c7aStrem ldr r6,=0x7 /* load loop counter */ 139*bcc05c7aStrem1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 140*bcc05c7aStrem subs r6,r6,#1 141*bcc05c7aStrem bne 1b 142*bcc05c7aStrem 143*bcc05c7aStrem ldr r1, =ACFG_SET_MODE_REG_CMD 144*bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 145*bcc05c7aStrem 146*bcc05c7aStrem /* set standard mode register */ 147*bcc05c7aStrem ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL 148*bcc05c7aStrem strb r2, [r4] 149*bcc05c7aStrem 150*bcc05c7aStrem /* set extended mode register */ 151*bcc05c7aStrem ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 152*bcc05c7aStrem strb r2, [r4] 153*bcc05c7aStrem 154*bcc05c7aStrem ldr r1, =ACFG_NORMAL_RW_CMD 155*bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 156*bcc05c7aStrem .endm /* init_ddr */ 157*bcc05c7aStrem 158*bcc05c7aStrem.globl lowlevel_init 159*bcc05c7aStremlowlevel_init: 160*bcc05c7aStrem 161*bcc05c7aStrem init_aipi 162*bcc05c7aStrem init_clock 163*bcc05c7aStrem#ifdef CONFIG_SPL_BUILD 164*bcc05c7aStrem init_ddr 165*bcc05c7aStrem#endif 166*bcc05c7aStrem 167*bcc05c7aStrem mov pc, lr 168